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to our customers, old company name in catalogs and other documents on april 1 st , 2010, nec electronics corporation merged with renesas technology corporation, and renesas electronics corporation took over all the business of both companies. therefore, although the old company name remains in this document, it is a valid renesas electronics document. we appreciate your understanding. renesas electronics website: http://www.renesas.com april 1 st , 2010 renesas electronics corporation issued by: renesas electronics corporation ( http://www.renesas.com ) send any inquiries to http://www.renesas.com/inquiry .
notice 1. all information included in this document is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas electronics products listed herein, please confirm the latest product information with a renesas electronics sales office. also, please pay regular and careful attention to additional and different information to be disclosed by renesas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electronics products or technical information described in this document . no license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property right s of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part . 4. descriptions of circuits, software and other related information in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. you should not use renesas electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. renesas electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 7. renesas electronics products are classified according to the following three quality grades: ?standard?, ?high quality?, an d ?specific?. the recommended applications for each renesas electronics product depends on the product?s quality grade, as indicated below. you must check the quality grade of each renesas electronics product before using it in a particular application. you may not use any renesas electronics product for any application categorized as ?specific? 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h8/36079 group, h8/36077 group hardware manual 16 users manual rev.3.00 2007.09 renesas 16-bit single-chip microcomputer h8 family/h8/300h tiny series h8/36079 h8/36079gf, hd64f36079g h8/36079lf, hd64f36079l h8/36078gf, hd64f36078g h8/36078lf, hd64f36078l h8/36077 h8/36077gf, hd64f36077g h8/36077lf, hd64f36077l h8/36074gf, HD64F36074G h8/36074lf, hd64f36074l
rev. 3.00 sep. 10, 2007 page ii of xxxii
rev. 3.00 sep. 10, 2007 page iii of xxxii 1. this document is provided for reference purposes only so that renesas customers may select the appropriate renesas products for their use. renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of renesas or any third party with respect to the information in this document. 2. renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. you should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. when exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. all information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas products listed in this document, please confirm the latest product information with a renesas sales office. also, please pay regular and careful attention to additional and different information to be disclosed by renesas such as that disclosed through our website. (http://www.renesas.com ) 5. renesas has used reasonable care in compiling the information included in this document, but renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. when using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or renesas products. 7. with the exception of products specified by renesas as suitable for automobile applications, renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. if you are considering the use of our products for such purposes, please contact a renesas sales office beforehand. renesas shall have no liability for damages arising out of the uses set forth above. 8. notwithstanding the preceding paragraph, you should not use renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use renesas products in any of the foregoing applications shall indemnify and hold harmless renesas technology corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. you should use the products described herein within the range specified by renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas shall have no liability for malfunctions or damages arising out of the use of renesas products beyond such specified ranges. 10. although renesas endeavors to improve the quality and reliability of its products, ic products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. in case renesas products listed in this document are detached from the products to which the renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. you should implement safety measures so that renesas products may not be easily detached from your products. renesas shall have no liability for damages arising out of such detachment. 12. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from renesas. 13. please contact a renesas sales office if you have any questions regarding the information contained in this document, renesas semiconductor products, or if you have any other inquiries. notes regarding these materials
rev. 3.00 sep. 10, 2007 page iv of xxxii general precautions on handling of product 1. treatment of nc pins note: do not connect anything to the nc pins. the nc (not connected) pins are either not conn ected to any of the internal circuitry or are used as test pins or to reduce noise. if something is connected to the nc pins, the operation of the lsi is not guaranteed. 2. treatment of unused input pins note: fix all unused input pins to high or low level. generally, the input pins of cmos products are high-impedance input pins. if unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a pass- through current flows internally, and a malfunction may occur. 3. processing before initialization note: when power is first supplied, the product's state is undefined. the states of internal circuits are undefine d until full power is supplied throughout the chip and a low level is input on the reset pin. during the period where the states are undefined, the register settings and the output state of each pi n are also undefined. design your system so that it does not malfunction because of processing while it is in this undefined state. for those products which have a reset function, reset the lsi immediately after the power supply has been turned on. 4. prohibition of access to undefined or reserved addresses note: access to undefined or reserved addresses is prohibited. the undefined or reserved addresses may be us ed to expand functions, or test registers may have been be allocated to these addresse s. do not access these registers; the system's operation is not guaranteed if they are accessed.
rev. 3.00 sep. 10, 2007 page v of xxxii configuration of this manual this manual comprises the following items: 1. general precautions on handling of product 2. configuration of this manual 3. preface 4. contents 5. overview 6. description of functional modules ? cpu and system-control modules on-chip peripheral modules the configuration of the functional descrip tion of each module differs according to the module. however, the generic style includes the following items: i) feature ii) input/output pin iii) register description iv) operation v) usage note when designing an application system that includes this lsi, take notes into account. each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. list of registers 8. electrical characteristics 9. appendix 10. main revisions and additions in this edition (only for revised versions) the list of revisions is a summary of points that have been revised or added to earlier versions. this does not include all of the revised contents. for details, see the actual locations in this manual. 11. index
rev. 3.00 sep. 10, 2007 page vi of xxxii preface the h8/36079 group and h8/36077 group are single-chip microcomputers made up of the high- speed h8/300h cpu employing renesas technology original architecture as their cores, and the peripheral functions required to configure a system. the h8/300h cpu has an instruction set that is compatible with the h8/300 cpu. target users: this manual was written for us ers who will be using the h8/36079 group and h8/36077 group in the design of application systems. target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. objective: this manual was written to explain the hardware functions and electrical characteristics of the h8/36079 group and h8/36077 group to the target users. refer to the h8/300h series software manual for a detailed description of the instruction set. notes on reading this manual: ? in order to understand the overall functions of the chip read the manual according to the contents. this manual can be roughly categorized into parts on the cpu, system control functions, peripher al functions and elect rical characteristics. ? in order to understand the details of the cpu's functions read the h8/300h series software manual. ? in order to understand the details of a register when its name is known read the index that is the final part of the manual to find the page number of the entry on the register. the addresses, bits, and initial values of the registers are summarized in section 21, list of registers. example: register name: the following notatio n is used for cases when the same or a similar function, e.g. serial communication interface, is implemented on more than one channel: xxx_n (xxx is the register name and n is the channel number) bit order: the msb is on the left and the lsb is on the right.
rev. 3.00 sep. 10, 2007 page vii of xxxii notes: when using an on-chip emulator (e7, e8) for h8/36079 and h8/36077 program development and debugging, the following restrictions must be noted. 1. the nmi pin is reserved for the e7 or e8, and cannot be used. 2. pins p85, p86, and p 87 cannot be used. in order to use thes e pins, additional hardware must be provided on the user board. 3. the following areas are used by the e7 or e8, and are not available to the user. h8/36079 group: h' 01f000 to h'01ffff h8/36077 group: h'd000 to h'dfff 4. the following areas must on no account be accessed. h8/36079 group: h'fff780 to h'fffb7f h8/36077 group: h'f780 to h'fb7f 5. in usage with the e7or e8, address breaks can be set as either available to the user or for use by the e7 or e8. if address breaks are set as being used by the e7, the address break control registers must not be accessed. 6. in usage with the e7 or e8, nmi is an input/output pin (open-drain in output mode), p85 and p87 are input pins, and p86 is an output pin. 7. use channel 1 of the sci3 (p21/rxd, p22/txd) in on-board programming mode by boot mode. 8. in usage with the e7or e8, the power supply voltage for h8/36079 group products must be greater than the reset detection voltage of the low voltage detection circuit. related manuals: the latest versions of all related manuals are available from our web site. please ensure you have the latest versions of all documents you require. http://www.renesas.com/
rev. 3.00 sep. 10, 2007 page viii of xxxii h8/36079 group and h8/36077 group manuals: document title document no. h8/36079 group, h8/36077 group hardware manual this manual h8/300h series software manual rej09b0213 user's manuals for development tools: document title document no. h8s, h8/300 series c/c++ compiler, assembler, optimizing linkage editor user's manual rej10b0058 h8s, h8/300 series simulator/debugger user's manual rej10b0211 h8s, h8/300 series high-performance embedded workshop 3, tutorial rej10b0024 h8s, h8/300 series high-performance embedded workshop 3, user's manual rej10b0026 application notes: document title document no. h8s, h8/300 series c/c++ compiler package application note rej05b0464 single power supply f-ztat tm on-board programming rej05b0520 all trademarks and registered trademarks are the property of their respective owners.
rev. 3.00 sep. 10, 2007 page ix of xxxii contents section 1 overview..................................................................................................1 1.1 features....................................................................................................................... .......... 1 1.2 block diagram.................................................................................................................. .... 4 1.3 pin arrangement ................................................................................................................ ... 5 1.4 pin functions .................................................................................................................. ...... 6 section 2 cpu..........................................................................................................9 2.1 address space and memory map ....................................................................................... 11 2.2 register configuration........................................................................................................ 1 2 2.2.1 general registers ................................................................................................ 13 2.2.2 program counter (pc) ........................................................................................ 14 2.2.3 condition-code register (ccr) ......................................................................... 14 2.3 data formats................................................................................................................... .... 16 2.3.1 general register data formats ........................................................................... 16 2.3.2 memory data formats ........................................................................................ 18 2.4 instruction set ................................................................................................................ ..... 19 2.4.1 table of instructions classified by function ...................................................... 19 2.4.2 basic instruction formats ................................................................................... 29 2.5 addressing modes and effective address calculation....................................................... 30 2.5.1 addressing modes .............................................................................................. 30 2.5.2 effective address calculation ............................................................................ 33 2.6 basic bus cycle ................................................................................................................ .. 36 2.6.1 access to on-chip memory (ram, rom)........................................................ 36 2.6.2 on-chip peripheral modules .............................................................................. 37 2.7 cpu states ..................................................................................................................... ..... 38 2.8 usage notes .................................................................................................................... .... 39 2.8.1 notes on data access to empty areas ............................................................... 39 2.8.2 eepmov instruction.......................................................................................... 39 2.8.3 bit-manipulation instruction............................................................................... 40 section 3 exception handling ...............................................................................45 3.1 exception sources and vector address .............................................................................. 46 3.2 register descriptions .......................................................................................................... 48 3.2.1 interrupt edge select register 1 (iegr1) .......................................................... 48 3.2.2 interrupt edge select register 2 (iegr2) .......................................................... 49 3.2.3 interrupt enable register 1 (ienr1) .................................................................. 50
rev. 3.00 sep. 10, 2007 page x of xxxii 3.2.4 interrupt enable register 2 (ienr2) .................................................................. 51 3.2.5 interrupt flag register 1 (irr1)......................................................................... 51 3.2.6 interrupt flag register 2 (irr2)......................................................................... 53 3.2.7 wakeup interrupt flag register (iwpr) ............................................................ 53 3.3 reset exception handling .................................................................................................. 55 3.4 interrupt exception handling ............................................................................................. 56 3.4.1 external interrupts .............................................................................................. 56 3.4.2 internal interrupts ............................................................................................... 58 3.4.3 interrupt handling sequence .............................................................................. 58 3.4.4 interrupt res ponse time..................................................................................... 60 3.5 usage notes .................................................................................................................... .... 62 3.5.1 interrupts after reset........................................................................................... 62 3.5.2 notes on stack area use .................................................................................... 62 3.5.3 notes on rewriting port mode registers ........................................................... 62 section 4 address break ....................................................................................... 63 4.1 register descriptions.......................................................................................................... 64 4.1.1 address break control register (abrkcr) ..................................................... 64 4.1.2 address break status register (abrksr) ........................................................ 67 4.1.3 break address registers (bare, barh, barl) ............................................. 67 4.1.4 break data registers (bdrh, bdrl) ............................................................... 67 4.2 operation ...................................................................................................................... ...... 68 section 5 clock pulse generator ........................................................................... 71 5.1 features....................................................................................................................... ........ 72 5.2 register descriptions.......................................................................................................... 72 5.2.1 rc control register (rccr) ............................................................................. 73 5.2.2 rc trimming data protect register (rctrmdpr).......................................... 74 5.2.3 rc trimming data register (rctrmdr) ........................................................ 75 5.2.4 clock control/status register (ckcsr) ............................................................ 76 5.3 system clock select operation .......................................................................................... 79 5.3.1 clock control operation..................................................................................... 79 5.3.2 clock switching timing..................................................................................... 83 5.4 trimming of on-chip os cillator frequency ...................................................................... 86 5.5 external os cillato rs........................................................................................................... .. 88 5.5.1 connecting crystal resonator ............................................................................ 88 5.5.2 connecting ceramic resonator .......................................................................... 89 5.5.3 inputting external clock..................................................................................... 89 5.6 subclock os cillator............................................................................................................ .90 5.6.1 connecting 32.768-khz crystal resonator......................................................... 90
rev. 3.00 sep. 10, 2007 page xi of xxxii 5.6.2 pin connection when not using subclock......................................................... 91 5.7 prescaler...................................................................................................................... ........ 91 5.7.1 prescaler s........................................................................................................... 91 5.7.2 prescaler w ......................................................................................................... 91 5.8 usage notes .................................................................................................................... .... 92 5.8.1 note on resonators ............................................................................................. 92 5.8.2 notes on board design ....................................................................................... 92 section 6 power-down modes ..............................................................................93 6.1 register descriptions .......................................................................................................... 94 6.1.1 system control register 1 (syscr1) ................................................................ 94 6.1.2 system control register 2 (syscr2) ................................................................ 97 6.1.3 module standby control re gister 1 (mstcr1)................................................. 98 6.1.4 module standby control re gister 2 (mstcr2)................................................. 99 6.2 mode transitions and states of lsi.................................................................................. 100 6.2.1 sleep mode ....................................................................................................... 103 6.2.2 standby mo de ................................................................................................... 103 6.2.3 subsleep mode.................................................................................................. 104 6.2.4 subactive mode ................................................................................................ 104 6.3 operating frequency in active mode............................................................................... 105 6.4 direct tr ansition .............................................................................................................. . 105 6.4.1 direct transition from active mode to subactive mode.................................. 105 6.4.2 direct transition from subact ive mode to active mode.................................. 106 6.5 module standby function................................................................................................. 106 section 7 rom ....................................................................................................107 7.1 block confi guration ......................................................................................................... 107 7.2 register descriptions ........................................................................................................ 11 2 7.2.1 flash memory control register 1 (flmcr1).................................................. 112 7.2.2 flash memory control register 2 (flmcr2).................................................. 113 7.2.3 erase block regist er 1 (e br1) ........................................................................ 114 7.2.4 flash memory power control register (flpwcr) ......................................... 116 7.2.5 flash memory enable register (fenr) ........................................................... 116 7.3 on-board programming modes........................................................................................ 117 7.3.1 boot m ode ........................................................................................................ 117 7.3.2 programming/erasing in user program mode.................................................. 120 7.4 flash memory programming/erasing............................................................................... 121 7.4.1 program/program-verify .................................................................................. 121 7.4.2 erase/erase-verify............................................................................................ 124 7.4.3 interrupt handling wh en programming/erasing flash memory....................... 124
rev. 3.00 sep. 10, 2007 page xii of xxxii 7.5 program/erase protection ................................................................................................. 126 7.5.1 hardware protection ......................................................................................... 126 7.5.2 software protection........................................................................................... 126 7.5.3 error protection................................................................................................. 126 7.6 programmer mode ............................................................................................................ 127 7.7 power-down states for flash memory............................................................................. 127 section 8 ram .................................................................................................... 129 section 9 i/o ports............................................................................................... 131 9.1 port 1......................................................................................................................... ........ 131 9.1.1 port mode register 1 (pmr1) .......................................................................... 132 9.1.2 port control register 1 (pcr1) ........................................................................ 133 9.1.3 port data register 1 (pdr1)............................................................................. 133 9.1.4 port pull-up control register 1 (pucr1)........................................................ 134 9.1.5 pin functions .................................................................................................... 134 9.2 port 2......................................................................................................................... ........ 137 9.2.1 port control register 2 (pcr2) ........................................................................ 137 9.2.2 port data register 2 (pdr2)............................................................................. 138 9.2.3 port mode register 3 (pmr3) .......................................................................... 138 9.2.4 pin functions .................................................................................................... 139 9.3 port 3......................................................................................................................... ........ 141 9.3.1 port control register 3 (pcr3) ........................................................................ 141 9.3.2 port data register 3 (pdr3)............................................................................. 142 9.3.3 pin functions .................................................................................................... 142 9.4 port 5......................................................................................................................... ........ 145 9.4.1 port mode register 5 (pmr5) .......................................................................... 146 9.4.2 port control register 5 (pcr5) ........................................................................ 147 9.4.3 port data register 5 (pdr5)............................................................................. 147 9.4.4 port pull-up control register 5 (pucr5)........................................................ 148 9.4.5 pin functions .................................................................................................... 148 9.5 port 6......................................................................................................................... ........ 151 9.5.1 port control register 6 (pcr6) ........................................................................ 151 9.5.2 port data register 6 (pdr6)............................................................................. 152 9.5.3 pin functions .................................................................................................... 152 9.6 port 7......................................................................................................................... ........ 156 9.6.1 port control register 7 (pcr7) ........................................................................ 156 9.6.2 port data register 7 (pdr7)............................................................................. 157 9.6.3 pin functions .................................................................................................... 157 9.7 port 8......................................................................................................................... ........ 159
rev. 3.00 sep. 10, 2007 page xiii of xxxii 9.7.1 port control register 8 (pcr8) ........................................................................ 159 9.7.2 port data register 8 (pdr8)............................................................................. 159 9.7.3 pin functions .................................................................................................... 160 9.8 port b ......................................................................................................................... ....... 161 9.8.1 port data register b (pdrb) ........................................................................... 161 9.8.2 pin functions .................................................................................................... 162 9.9 port c ......................................................................................................................... ....... 165 9.9.1 port control register c (pcrc)....................................................................... 165 9.9.2 port data register c (pdrc) ........................................................................... 166 9.9.3 pin functions .................................................................................................... 166 section 10 realtime clock (rtc) .......................................................................167 10.1 features....................................................................................................................... ...... 167 10.2 input/output pin ............................................................................................................... 168 10.3 register descriptions ........................................................................................................ 16 9 10.3.1 second data register/free running counter data register (rsecdr).......... 169 10.3.2 minute data register (rmindr)..................................................................... 170 10.3.3 hour data register (rhrdr) .......................................................................... 171 10.3.4 day-of-week data register (rwkdr) ........................................................... 172 10.3.5 rtc control regist er 1 (rt ccr1) .................................................................. 173 10.3.6 rtc control regist er 2 (rt ccr2) .................................................................. 174 10.3.7 clock source select register (rtccsr) ......................................................... 175 10.4 operation ...................................................................................................................... .... 176 10.4.1 initial settings of regist ers after power-on ..................................................... 176 10.4.2 initial setting procedure ................................................................................... 176 10.4.3 data reading procedure ................................................................................... 177 10.5 interrupt sources.............................................................................................................. . 178 section 11 timer b1 ............................................................................................179 11.1 features....................................................................................................................... ...... 179 11.2 input/output pin ............................................................................................................... 180 11.3 register descriptions ........................................................................................................ 18 1 11.3.1 timer mode register b1 (tmb1) .................................................................... 181 11.3.2 timer counter b1 (tcb1)................................................................................ 182 11.3.3 timer load register b1 (tlb1)....................................................................... 182 11.4 operation ...................................................................................................................... .... 182 11.4.1 interval timer operation .................................................................................. 182 11.4.2 auto-reload timer operation .......................................................................... 183 11.4.3 event counter operation .................................................................................. 183 11.5 timer b1 operating modes .............................................................................................. 183
rev. 3.00 sep. 10, 2007 page xiv of xxxii section 12 timer v ............................................................................................. 185 12.1 features....................................................................................................................... ...... 185 12.2 input/output pins.............................................................................................................. 187 12.3 register descriptions........................................................................................................ 18 7 12.3.1 timer counter v (tcntv) .............................................................................. 187 12.3.2 time constant registers a and b (tcora, tcorb) .................................... 188 12.3.3 timer control register v0 (tcrv0) ............................................................... 188 12.3.4 timer control/status register v (tcsrv) ...................................................... 189 12.3.5 timer control register v1 (tcrv1) ............................................................... 191 12.4 operation ...................................................................................................................... .... 192 12.4.1 timer v operation............................................................................................ 192 12.5 timer v applica tion examples ........................................................................................ 195 12.5.1 pulse output with arb itrary duty cycle........................................................... 195 12.5.2 pulse output with arbitrary pulse width and delay from trgv input .......... 196 12.6 usage notes .................................................................................................................... .. 197 section 13 timer z.............................................................................................. 199 13.1 features....................................................................................................................... ...... 199 13.2 input/output pins.............................................................................................................. 204 13.3 register descriptions........................................................................................................ 20 5 13.3.1 timer start register (tstr) ............................................................................ 206 13.3.2 timer mode register (tmdr)......................................................................... 206 13.3.3 timer pwm mode register (tpmr) ............................................................... 207 13.3.4 timer function control register (tfcr) ........................................................ 208 13.3.5 timer output master enable register (toer) ................................................ 210 13.3.6 timer output control register (tocr) ........................................................... 212 13.3.7 timer counter (tcnt)..................................................................................... 213 13.3.8 general registers a, b, c, and d (gra, grb, grc, and grd).................... 213 13.3.9 timer control register (tcr).......................................................................... 214 13.3.10 timer i/o control register (tiora and tiorc)............................................ 215 13.3.11 timer status register (tsr)............................................................................. 218 13.3.12 timer interrupt enable register (tier)........................................................... 220 13.3.13 pwm mode output level co ntrol register (pocr) ....................................... 221 13.3.14 interface with cpu ........................................................................................... 222 13.4 operation ...................................................................................................................... .... 223 13.4.1 counter operation............................................................................................. 223 13.4.2 waveform output by compare match.............................................................. 227 13.4.3 input capture function ..................................................................................... 229 13.4.4 synchronous op eration..................................................................................... 233 13.4.5 pwm mode ...................................................................................................... 234
rev. 3.00 sep. 10, 2007 page xv of xxxii 13.4.6 reset synchronous pwm mode ....................................................................... 240 13.4.7 complementary pwm mode ............................................................................ 244 13.4.8 buffer operation ............................................................................................... 254 13.4.9 timer z output timing .................................................................................... 262 13.5 interrupts..................................................................................................................... ...... 265 13.5.1 status flag set timing...................................................................................... 265 13.5.2 status flag cl earing timing ............................................................................. 267 13.6 usage notes .................................................................................................................... .. 268 section 14 watchdog timer ................................................................................275 14.1 features....................................................................................................................... ...... 275 14.2 register descriptions ........................................................................................................ 27 6 14.2.1 timer control/status register wd (tcsrwd)............................................... 276 14.2.2 timer counter wd (tcwd)............................................................................ 278 14.2.3 timer mode register wd (tmwd) ................................................................ 278 14.3 operation ...................................................................................................................... .... 279 section 15 14-bit pwm.......................................................................................281 15.1 features....................................................................................................................... ...... 281 15.2 input/output pin ............................................................................................................... 282 15.3 register descriptions ........................................................................................................ 28 3 15.3.1 pwm control register (pwcr)....................................................................... 283 15.3.2 pwm data registers u and l (pwdru, pwdrl)......................................... 283 15.4 operation ...................................................................................................................... .... 284 section 16 serial communica tion interface 3 (sci3) .........................................285 16.1 features....................................................................................................................... ...... 285 16.2 input/output pins.............................................................................................................. 288 16.3 register descriptions ........................................................................................................ 28 9 16.3.1 receive shift register (rsr) ........................................................................... 289 16.3.2 receive data register (rdr) ........................................................................... 289 16.3.3 transmit shift register (tsr) .......................................................................... 289 16.3.4 transmit data register (tdr).......................................................................... 290 16.3.5 serial mode register (smr)............................................................................. 290 16.3.6 serial control regi ster 3 (s cr3) ...................................................................... 292 16.3.7 serial status register (ssr) ............................................................................. 294 16.3.8 bit rate register (brr) ................................................................................... 296 16.4 operation in async hronous mode .................................................................................... 303 16.4.1 clock................................................................................................................. 303 16.4.2 sci3 initialization............................................................................................. 304
rev. 3.00 sep. 10, 2007 page xvi of xxxii 16.4.3 data transmission ............................................................................................ 305 16.4.4 serial data reception ....................................................................................... 307 16.5 operation in clock synchronous mode............................................................................ 311 16.5.1 clock................................................................................................................. 311 16.5.2 sci3 initialization............................................................................................. 311 16.5.3 serial data transmission .................................................................................. 312 16.5.4 serial data reception (clock synchronous mode) .......................................... 314 16.5.5 simultaneous serial data tr ansmission and reception.................................... 316 16.6 multiprocessor communication function ........................................................................ 318 16.6.1 multiprocessor serial da ta transmission ......................................................... 319 16.6.2 multiprocessor serial data reception .............................................................. 321 16.7 interrupts..................................................................................................................... ...... 325 16.8 usage notes .................................................................................................................... .. 326 16.8.1 break detection and processing ....................................................................... 326 16.8.2 mark state and break sending ......................................................................... 326 16.8.3 receive error flags and transmit operations (clock synchronous mode only) ..................................................................... 326 16.8.4 receive data sampling timing and reception margin in asynchronous mode......................................................................................... 327 section 17 i 2 c bus interface 2 (iic2).................................................................. 329 17.1 features....................................................................................................................... ...... 329 17.2 input/output pins.............................................................................................................. 331 17.3 register descriptions........................................................................................................ 33 2 17.3.1 i 2 c bus control regi ster 1 (i ccr1) ................................................................. 332 17.3.2 i 2 c bus control regi ster 2 (i ccr2) ................................................................. 335 17.3.3 i 2 c bus mode register (icmr)........................................................................ 336 17.3.4 i 2 c bus interrupt enable register (icier) ....................................................... 338 17.3.5 i 2 c bus status register (icsr)......................................................................... 340 17.3.6 slave address register (sar).......................................................................... 343 17.3.7 i 2 c bus transmit data register (icdrt)......................................................... 344 17.3.8 i 2 c bus receive data register (icdrr).......................................................... 344 17.3.9 i 2 c bus shift register (icdrs)........................................................................ 344 17.4 operation ...................................................................................................................... .... 345 17.4.1 i 2 c bus format.................................................................................................. 345 17.4.2 master transmit operation ............................................................................... 346 17.4.3 master receive operation................................................................................. 348 17.4.4 slave transmit operation ................................................................................. 350 17.4.5 slave receive operation................................................................................... 352 17.4.6 clock synchronous serial format .................................................................... 354
rev. 3.00 sep. 10, 2007 page xvii of xxxii 17.4.7 noise f ilter ....................................................................................................... 357 17.4.8 example of use................................................................................................. 357 17.5 interrupt request.............................................................................................................. . 362 17.6 bit synchronous circuit.................................................................................................... 363 17.7 usage notes .................................................................................................................... .. 364 17.7.1 issue (retransmission) of start/stop conditions .............................................. 364 17.7.2 wait setting in i 2 c bus mode register (icmr) ............................................ 364 17.7.3 restriction in use of multi-master ................................................................... 365 17.7.4 continuous data reception in master receive mode ...................................... 365 section 18 a/d converter....................................................................................367 18.1 features....................................................................................................................... ...... 367 18.2 input/output pins.............................................................................................................. 369 18.3 register descriptions ........................................................................................................ 37 0 18.3.1 a/d data registers a to d (addra to addrd) .......................................... 370 18.3.2 a/d control/status register (adcsr) ............................................................ 371 18.3.3 a/d control register (adcr) ......................................................................... 372 18.4 operation ...................................................................................................................... .... 373 18.4.1 single mode...................................................................................................... 373 18.4.2 scan mode ........................................................................................................ 373 18.4.3 input sampling and a/ d conversi on time ....................................................... 374 18.4.4 external trigger input ti ming.......................................................................... 375 18.5 a/d conversion accuracy definitions ............................................................................. 376 18.6 usage notes .................................................................................................................... .. 378 18.6.1 permissible signal s ource impedance .............................................................. 378 18.6.2 influences on absolute accuracy ..................................................................... 378 section 19 band-gap circuit, power-on reset, and low-voltage detection circuits........................................................379 19.1 features....................................................................................................................... ...... 380 19.2 register descriptions ........................................................................................................ 38 2 19.2.1 low-voltage-detection cont rol register (lvdcr) ........................................ 382 19.2.2 low-voltage-detection stat us register (lvdsr)........................................... 384 19.2.3 reset source decision register (lvdrf)........................................................ 385 19.3 operations..................................................................................................................... .... 386 19.3.1 power-on reset circuit .................................................................................... 386 19.3.2 low-voltage detection circuit......................................................................... 387 19.3.3 deciding reset source...................................................................................... 392
rev. 3.00 sep. 10, 2007 page xviii of xxxii section 20 power supply circuit ........................................................................ 393 20.1 power supply connection of 5.0-v-specification microcontrollers ................................ 393 20.2 power supply connection of 3.3-v-specification microcontrollers ................................ 394 section 21 list of registers................................................................................. 395 21.1 register addresses (address order)................................................................................. 396 21.2 register bits.................................................................................................................. .... 403 21.3 registers states in each operating mode......................................................................... 409 section 22 electrical characteristics ................................................................... 415 22.1 absolute maximum ratings ............................................................................................. 415 22.2 electrical characteristics (f -ztat? 5.0-v version) ..................................................... 416 22.2.1 power supply voltage a nd operating ranges .................................................. 416 22.2.2 dc characteristics ............................................................................................ 419 22.2.3 ac characteristics ............................................................................................ 425 22.2.4 a/d converter characteristics .......................................................................... 430 22.2.5 watchdog timer char acteristics....................................................................... 431 22.2.6 flash memory characteristics .......................................................................... 432 22.2.7 power-supply-voltage detection circuit characteristics................................. 434 22.2.8 lvdi external input voltage detection circuit characteristics ...................... 434 22.2.9 power-on reset circuit characteristics ........................................................... 435 22.3 electrical characteristics (f -ztat? 3.3-v version) ..................................................... 436 22.3.1 power supply voltage a nd operating ranges .................................................. 436 22.3.2 dc characteristics ............................................................................................ 438 22.3.3 ac characteristics ............................................................................................ 444 22.3.4 a/d converter characteristics .......................................................................... 449 22.3.5 watchdog timer char acteristics....................................................................... 450 22.3.6 flash memory characteristics .......................................................................... 451 22.3.7 power-supply-voltage detection circuit characteristics................................. 453 22.3.8 lvdi external input voltage detection circuit characteristics ...................... 453 22.3.9 power-on reset circuit characteristics ........................................................... 454 22.4 operation timing.............................................................................................................. 4 55 22.5 output load condition ..................................................................................................... 458 appendix a instruction set ............................................................................... 459 a.1 instruction list............................................................................................................... ... 459 a.2 operation code map......................................................................................................... 474 a.3 number of execution states ............................................................................................. 477 a.4 combinations of instructi ons and addre ssing mode s ...................................................... 488
rev. 3.00 sep. 10, 2007 page xix of xxxii appendix b i/o port block diagrams ...............................................................489 b.1 i/o port block diagrams .................................................................................................. 489 b.2 port states in each operating state .................................................................................. 513 appendix c produc t code lineup.....................................................................514 appendix d package dimensions .....................................................................516 main revisions and additions in this edition .....................................................519 index ....................................................................................................................525
rev. 3.00 sep. 10, 2007 page xx of xxxii
rev. 3.00 sep. 10, 2007 page xxi of xxxii figures section 1 overview figure 1.1 block diagram of h8 /36079 group and h8 /36077 group ........................................... 4 figure 1.2 pin arrangement of h8/36079 group and h8/36077 group (f p-64k, fp-64a) ............................................................................ 5 section 2 cpu figure 2.1 memory map........................................................................................................ ....... 11 figure 2.2 cpu registers ..................................................................................................... ........ 12 figure 2.3 usage of general registers ........................................................................................ .13 figure 2.4 relationship between stack pointer and stack area ................................................... 14 figure 2.5 general register data formats (1).............................................................................. 16 figure 2.5 general register data formats (2).............................................................................. 17 figure 2.6 memory data formats............................................................................................... .. 18 figure 2.7 instruction formats............................................................................................... ....... 29 figure 2.8 branch address specification in memory indirect mode ........................................... 33 figure 2.9 on-chip memory access cycle.................................................................................. 36 figure 2.10 on-chip peripheral module access cycle (3-state access)..................................... 37 figure 2.11 cpu operation states............................................................................................. ... 38 figure 2.12 state transitions ................................................................................................ ........ 39 figure 2.13 example of timer configuration with two registers allocated to same address ....................................................................................... 40 section 3 exception handling figure 3.1 reset sequence.................................................................................................... ........ 57 figure 3.2 stack status after exception handling ........................................................................ 59 figure 3.3 interrupt sequence................................................................................................ ....... 61 figure 3.4 port mode register setting and interrupt request flag clearing procedure .............. 62 section 4 address break figure 4.1 block diagram of address break................................................................................ 63 figure 4.2 address break interrupt operation example (1)......................................................... 68 figure 4.2 address break interrupt operation example (2)......................................................... 69 section 5 clock pulse generator figure 5.1 block diagram of clock pulse generator ................................................................... 71 figure 5.2 state trans ition of system clock ................................................................................ 79 figure 5.3 flowchart of clock switching with backup function enabled................................... 80 figure 5.4 flowchart of clock switching with backup function disabled (1) (from on-chip oscillator clock to external clock) ................................................. 81
rev. 3.00 sep. 10, 2007 page xxii of xxxii figure 5.5 flowchart of clock switching with backup function disabled (2) (from external clock to on-chip oscillator clock).................................................. 82 figure 5.6 timing chart of switching from on-chip oscillator clock to external clock............................................................................................................ 83 figure 5.7 timing chart to switch from external clock to on-chip oscillator clock .......................................................................................................... 84 figure 5.8 external oscillation backup timing ........................................................................... 85 figure 5.9 example of trimming fl ow for on-chip oscillator clock ........................................ 86 figure 5.10 timing chart of trimming of on-chip oscillator frequency .................................. 87 figure 5.11 block diagram of external clock oscillator ............................................................ 88 figure 5.12 example of connection to crystal resonator ........................................................... 88 figure 5.13 equivalent circuit of crystal resonator.................................................................... 89 figure 5.14 example of connection to ceramic resonator ......................................................... 89 figure 5.15 example of external clock input .............................................................................. 89 figure 5.16 block diagram of subclock oscillator...................................................................... 90 figure 5.17 typical connection to 32.768-khz crystal resonator.............................................. 90 figure 5.18 equivalent circuit of 32.768-khz crystal resonator................................................ 90 figure 5.19 pin connection when not using subclock ................................................................ 91 figure 5.20 example of incorrect board design .......................................................................... 92 section 6 power-down modes figure 6.1 mode transition diagram ......................................................................................... 10 0 section 7 rom figure 7.1 flash memory block configuration (1) (h8/36079gf and h8/36079lf) ............... 108 figure 7.1 flash memory block configuration (2) (h8/36078gf and h8/36078lf) ............... 109 figure 7.1 flash memory block configuration (3) (h8/36077gf and h8/36077lf) ............... 110 figure 7.1 flash memory block configuration (4) (h8/36074gf and h8/36074lf) ............... 111 figure 7.2 programming/erasing flowchart example in user program mode .......................... 120 figure 7.3 program/prog ram-verify flowchart ......................................................................... 122 figure 7.4 erase/erase-verify flowchart ................................................................................... 125 section 9 i/o ports figure 9.1 port 1 pin configuration.......................................................................................... .. 131 figure 9.2 port 2 pin configuration.......................................................................................... .. 137 figure 9.3 port 3 pin configuration.......................................................................................... .. 141 figure 9.4 port 5 pin configuration.......................................................................................... .. 145 figure 9.5 port 6 pin configuration.......................................................................................... .. 151 figure 9.6 port 7 pin configuration.......................................................................................... .. 156 figure 9.7 port 8 pin configuration.......................................................................................... .. 159 figure 9.8 port b pin configuration.......................................................................................... . 161 figure 9.9 port c pin configuration.......................................................................................... . 165
rev. 3.00 sep. 10, 2007 page xxiii of xxxii section 10 realtime clock (rtc) figure 10.1 block diagram of rtc ........................................................................................... 16 7 figure 10.2 definition of time expression ................................................................................ 173 figure 10.3 initial setting procedure ........................................................................................ .. 176 figure 10.4 example: reading of inaccurate time data............................................................ 177 section 11 timer b1 figure 11.1 block di agram of ti mer b1 .................................................................................... 179 section 12 timer v figure 12.1 block diagram of timer v...................................................................................... 186 figure 12.2 increment timing with internal clock .................................................................... 193 figure 12.3 increment timing with external clock ................................................................... 193 figure 12.4 ovf set timing ................................................................................................... ... 193 figure 12.5 cmfa and cmfb set timing ................................................................................ 194 figure 12.6 tmov output timing ............................................................................................ 194 figure 12.7 clear timing by compare match............................................................................ 194 figure 12.8 clear timing by tmriv input ............................................................................... 195 figure 12.9 pulse output example ............................................................................................. 195 figure 12.10 example of pulse output synchronized to trgv input....................................... 196 figure 12.11 contention between tcntv write and clear ...................................................... 197 figure 12.12 contention between tcora write and compare match ..................................... 198 figure 12.13 internal clock switching and tcntv operation ................................................. 198 section 13 timer z figure 13.1 timer z block diagram .......................................................................................... 20 1 figure 13.2 timer z (channel 0) block diagram ...................................................................... 202 figure 13.3 timer z (channel 1) block diagram ...................................................................... 203 figure 13.4 example of outputs in reset synchronous pwm mode and complementary pwm mode.................................................................................. 210 figure 13.5 accessing operation of 16-bit register (between cpu and tcnt (16 bits)) ....................................................................... 222 figure 13.6 accessing operation of 8-bit register (between cpu and tstr (8 bits)).......................................................................... 222 figure 13.7 example of counter operation setting procedure .................................................. 223 figure 13.8 free-running counter operation ............................................................................ 224 figure 13.9 periodic counter operation..................................................................................... 22 5 figure 13.10 count timing at internal clock operation............................................................ 225 figure 13.11 count timing at external clock operation (both edges detected)...................... 226 figure 13.12 example of setting procedure for waveform output by compare match................................................................................................ 227 figure 13.13 example of 0 output/1 output operation ............................................................. 228
rev. 3.00 sep. 10, 2007 page xxiv of xxxii figure 13.14 example of toggle output operatio n ................................................................... 228 figure 13.15 output compare timing ....................................................................................... 229 figure 13.16 example of input capture operation setting procedure ....................................... 230 figure 13.17 example of input capture operation .................................................................... 231 figure 13.18 input capture signal timing ................................................................................. 232 figure 13.19 example of synchronous operation setting procedure ........................................ 233 figure 13.20 example of synchronous operation...................................................................... 234 figure 13.21 example of pwm mode setting procedure .......................................................... 235 figure 13.22 example of pwm mode operation (1) ................................................................. 236 figure 13.23 example of pwm mode operation (2) ................................................................. 237 figure 13.24 example of pwm mode operation (3) ................................................................. 238 figure 13.25 example of pwm mode operation (4) ................................................................. 239 figure 13.26 example of reset synchronous pwm mode setting procedure........................... 241 figure 13.27 example of reset synchronous pwm mode operation (ols0 = ols1 = 1) .............................................................................................. 242 figure 13.28 example of reset synchronous pwm mode operation (ols0 = ols1 = 0) .............................................................................................. 243 figure 13.29 example of complementary pwm mode setting procedure................................ 245 figure 13.30 canceling procedure of complementary pwm mode.......................................... 246 figure 13.31 example of complementary pwm mode operation (1)....................................... 247 figure 13.32 (1) example of complementary pwm mode operation (tpsc2 = tpsc1 = tpsc0 = 0) (2)............................................................... 249 figure 13.32 (2) example of complementary pwm mode operation (tpsc2 = tpsc1 = tpsc0 0) (3)............................................................... 250 figure 13.33 timing of overshooting ........................................................................................ 25 1 figure 13.34 timing of undershooting ...................................................................................... 251 figure 13.35 compare match buffer operation......................................................................... 254 figure 13.36 input capt ure buffer operation............................................................................. 255 figure 13.37 example of buffer operation setting procedure................................................... 255 figure 13.38 example of buffer operation (1) (buffer operation for output compare register)................................................. 256 figure 13.39 example of compare match timing for buffer operation ................................... 257 figure 13.40 example of buffer operation (2) (buffer operation for input capture register) ..................................................... 258 figure 13.41 input capture timing of buffer operation............................................................ 259 figure 13.42 buffer operation (3) (buffer operation in complementary pwm mode cmd1 = cmd0 = 1) ........... 260 figure 13.43 buffer operation (4) (buffer operation in complementary pwm mode cmd1 = cmd0 = 1) ........... 261 figure 13.44 example of output disable timing of timer z by writing to toer .................. 262
rev. 3.00 sep. 10, 2007 page xxv of xxxii figure 13.45 example of output disable ti ming of timer z by external trigger.................... 263 figure 13.46 example of output inverse timing of timer z by writing to tfcr ................... 264 figure 13.47 example of output inverse timing of timer z by writing to pocr ................... 264 figure 13.48 imf flag set timing when compare match occurs ............................................ 265 figure 13.49 imf flag set timing at input capture .................................................................. 266 figure 13.50 ovf flag set timing ............................................................................................ 2 66 figure 13.51 status flag clearing timing.................................................................................. 267 figure 13.52 contention between tcnt write and clear operations....................................... 268 figure 13.53 contention between tcnt write and increment operations ............................... 269 figure 13.54 contention between gr write and compare match ............................................. 269 figure 13.55 contention between tcnt write and overflow................................................... 270 figure 13.56 contention between gr read and input capture.................................................. 271 figure 13.57 contention between count clearing and increment operations by input capture................................................................................................... 272 figure 13.58 contention between gr write and input capture................................................. 273 figure 13.59 when compare match and bit manipulation instruction to tocr occur at the same timing .................................................................................... 274 section 14 watchdog timer figure 14.1 block diagram of watchdog timer ........................................................................ 275 figure 14.2 watchdog ti mer operation example...................................................................... 279 section 15 14-bit pwm figure 15.1 block diagram of 14-bit pwm .............................................................................. 281 figure 15.2 waveform output by 14- bit pwm ......................................................................... 284 section 16 serial commun ication interface 3 (sci3) figure 16.1 block diagram of sci3 ........................................................................................... 2 87 figure 16.2 data format in asynchronous communication ...................................................... 303 figure 16.3 relationship between output clock and transfer data phase (asynchronous mode) (example with 8-bit data, parity, two stop bits)............. 303 figure 16.4 sample sci3 initialization flowchart ..................................................................... 304 figure 16.5 example of sci3 transmission in asynchronous mode (8-bit data, parity , one stop bit)........................................................................... 305 figure 16.6 sample serial transmission data flowchart (asynchronous mode)...................... 306 figure 16.7 example of sci3 reception in asynchronous mode (8-bit data, parity , one stop bit)........................................................................... 307 figure 16.8 sample serial reception da ta flowchart (asynchronous mode) (1)...................... 309 figure 16.8 sample serial reception da ta flowchart (asynchronous mode) (2)...................... 310 figure 16.9 data format in clock synchronous communication .............................................. 311 figure 16.10 example of sci3 transm ission in clock sy nchronous mode .............................. 312 figure 16.11 sample serial transmission flowchart (clock synchronous mode) .................... 313
rev. 3.00 sep. 10, 2007 page xxvi of xxxii figure 16.12 example of sci3 reception in clock synchronous mode.................................... 314 figure 16.13 sample serial reception flowchart (clock synchronous mode) ......................... 315 figure 16.14 sample flowchart of simultaneous serial transmit and receive operations (clock synchronous mode).................................................. 317 figure 16.15 example of inter-processor communication using multiprocessor format (transmission of data h' aa to receiving station a)............................. 319 figure 16.16 sample multiprocessor serial transmission flowchart ........................................ 320 figure 16.17 sample multiprocessor serial reception flowchart (1)........................................ 322 figure 16.17 sample multiprocessor serial reception flowchart (2)........................................ 323 figure 16.18 example of sci3 reception using multiprocessor format (example with 8-bit data, multiprocessor bit, one stop bit) ............................. 324 figure 16.19 receive data sampling timing in asynchronous mode ...................................... 327 section 17 i 2 c bus interface 2 (iic2) figure 17.1 block diagram of i 2 c bus interface 2..................................................................... 330 figure 17.2 external circu it connections of i/o pins ................................................................ 331 figure 17.3 i 2 c bus formats ...................................................................................................... 345 figure 17.4 i 2 c bus ti ming........................................................................................................ 345 figure 17.5 master transmit mode operation timing (1)......................................................... 347 figure 17.6 master transmit mode operation timing (2)......................................................... 347 figure 17.7 master receive mode operation timing (1) .......................................................... 349 figure 17.8 master receive mode operation timing (2) .......................................................... 350 figure 17.9 slave transmit mode operation timing (1) ........................................................... 351 figure 17.10 slave transmit mode operation timing (2) ......................................................... 352 figure 17.11 slave receive mode operation timing (1)........................................................... 353 figure 17.12 slave receive mode operation timing (2)........................................................... 353 figure 17.13 clock synchronous serial transfer format .......................................................... 354 figure 17.14 transmit mode operation timing......................................................................... 355 figure 17.15 receive mode operation timing .......................................................................... 356 figure 17.16 block diag ram of noise filter .............................................................................. 357 figure 17.17 sample flowchart for master transmit mode....................................................... 358 figure 17.18 sample flowchart for master receive mode ........................................................ 359 figure 17.19 sample flowchart for slave transmit mode......................................................... 360 figure 17.20 sample flowchart for slave receive mode .......................................................... 361 figure 17.21 the timing of th e bit synchronou s circuit .......................................................... 363 section 18 a/d converter figure 18.1 block diagram of a/d converter ........................................................................... 368 figure 18.2 a/d conversion timing.......................................................................................... 37 4 figure 18.3 external trigger input timing ................................................................................ 375 figure 18.4 a/d conversion accuracy definitions (1).............................................................. 377
rev. 3.00 sep. 10, 2007 page xxvii of xxxii figure 18.5 a/d conversion accuracy definitions (2) .............................................................. 377 figure 18.6 analog in put circuit example................................................................................. 378 section 19 band-gap circuit, power-on re set, and low-voltage detection circuits figure 19.1 block diagram around bgr ................................................................................... 380 figure 19.2 block diagram of power-on reset circuit and low-voltage detection circuit..................................................................................................... 381 figure 19.3 operational timing of power-on reset circuit ...................................................... 387 figure 19.4 operating timing of lvdr circuit ........................................................................ 388 figure 19.5 operational timing of lvdi circuit....................................................................... 389 figure 19.6 operational timing of lvdi circuit (when compared voltage is input through extu and extd pins) ......................... 391 figure 19.7 timing of setting bits in reset source decision register ...................................... 392 section 20 power supply circuit figure 20.1 power supply connection of 5.0-v-specification microcontrollers....................... 393 figure 20.2 power supply connection of 3.3-v-specification microcontrollers....................... 394 section 22 electrical characteristics figure 22.1 system clock input timing..................................................................................... 455 figure 22.2 res low width timing.......................................................................................... 455 figure 22.3 input timing..................................................................................................... ....... 455 figure 22.4 i 2 c bus interface input/output timing ................................................................... 456 figure 22.5 sck3 input clock timing....................................................................................... 456 figure 22.6 sci input/output timing in clock synchronous mode.......................................... 457 figure 22.7 output load circuit.............................................................................................. ... 458 appendix figure b.1 port 1 block diagram (p17) ..................................................................................... 489 figure b.2 port 1 bl ock diagram (p14, p16) ............................................................................. 490 figure b.3 port 1 block diagram (p15) ..................................................................................... 491 figure b.4 port 1 block diagram (p12) ..................................................................................... 492 figure b.5 port 2 block diagram (p11) ..................................................................................... 493 figure b.6 port 1 block diagram (p10) ..................................................................................... 494 figure b.7 port 2 bl ock diagram (p24, p23) ............................................................................. 495 figure b.8 port 2 block diagram (p22) ..................................................................................... 496 figure b.9 port 2 block diagram (p21) ..................................................................................... 497 figure b.10 port 2 block diagra m (p20) ................................................................................... 498 figure b.11 port 3 bloc k diagram (p37 to p30) ........................................................................ 499 figure b.12 port 5 bl ock diagram (p57, p56) ........................................................................... 500 figure b.13 port 5 block diagra m (p55) ................................................................................... 501 figure b.14 port 5 bloc k diagram (p54 to p50) ........................................................................ 502
rev. 3.00 sep. 10, 2007 page xxviii of xxxii figure b.15 port 6 bloc k diagram (p67 to p60) ........................................................................ 503 figure b.16 port 7 block diagra m (p76) ................................................................................... 504 figure b.17 port 7 block diagra m (p75) ................................................................................... 505 figure b.18 port 7 block diagra m (p74) ................................................................................... 506 figure b.19 port 7 block diagra m (p72) ................................................................................... 507 figure b.20 port 7 block diagra m (p71) ................................................................................... 508 figure b.21 port 7 block diagra m (p70) ................................................................................... 508 figure b.22 port 8 bloc k diagram (p87 to p85) ........................................................................ 509 figure b.23 port b bloc k diagram (pb7 and pb6) ................................................................... 510 figure b.24 port b bloc k diagram (pb5 to pb0) ...................................................................... 510 figure b.25 port b block diagram (pc1) .................................................................................. 511 figure b.26 port b block diagram (pc0) .................................................................................. 512 figure d.1 fp-64k package dimensions ................................................................................... 516 figure d.2 fp-64a package dimensions ................................................................................... 517
rev. 3.00 sep. 10, 2007 page xxix of xxxii tables section 1 overview table 1.1 pin functions ............................................................................................................ 6 section 2 cpu table 2.1 operation notation ................................................................................................. 19 table 2.2 data transfer instructions....................................................................................... 20 table 2.3 arithmetic operations instructions (1) ................................................................... 21 table 2.3 arithmetic operations instructions (2) ................................................................... 22 table 2.4 logic operations instructions................................................................................. 23 table 2.5 shift instructions..................................................................................................... 23 table 2.6 bit manipulation instructions (1)............................................................................ 24 table 2.6 bit manipulation instructions (2)............................................................................ 25 table 2.7 branch instructions ................................................................................................. 26 table 2.8 system control instructions.................................................................................... 27 table 2.9 block data transfer instructions ............................................................................ 28 table 2.10 addressing modes .................................................................................................. 30 table 2.11 absolute address access ranges ........................................................................... 32 table 2.12 effective address calculation (1)........................................................................... 34 table 2.12 effective address calculation (2)........................................................................... 35 section 3 exception handling table 3.1 exception sources and vector address .................................................................. 46 table 3.2 interrupt wait states ............................................................................................... 60 section 4 address break table 4.1 access and data bus used ..................................................................................... 66 section 5 clock pulse generator table 5.1 crystal resonator parameters ................................................................................. 89 section 6 power-down modes table 6.1 operating frequency and waiting time................................................................. 96 table 6.2 transition mode after sleep instruction execution and transition mode due to in terrupt...................................................................................................... 101 table 6.3 internal state in each operating mode................................................................. 102 section 7 rom table 7.1 setting programming modes ................................................................................ 117 table 7.2 boot mode operation ........................................................................................... 119
rev. 3.00 sep. 10, 2007 page xxx of xxxii table 7.3 system clock frequencies for which automatic adjustment of lsi bit rate is possible ..................................................................................................... 120 table 7.4 reprogram data computation table .................................................................... 123 table 7.5 additional-program data computation table ...................................................... 123 table 7.6 programming time ............................................................................................... 123 table 7.7 flash memory operating states............................................................................ 128 section 10 realtime clock (rtc) table 10.1 pin configuration.................................................................................................. 168 table 10.2 interrupt sources................................................................................................... 178 section 11 timer b1 table 11.1 pin configuration.................................................................................................. 180 table 11.2 timer b1 opera ting modes .................................................................................. 183 section 12 timer v table 12.1 pin configuration.................................................................................................. 187 table 12.2 clock signals to input to tcntv and counting conditions ............................... 189 section 13 timer z table 13.1 timer z functions ................................................................................................ 200 table 13.2 pin configuration.................................................................................................. 204 table 13.3 initial output level of ftiob0 pin...................................................................... 235 table 13.4 output pins in reset synchronous pwm mode ................................................... 240 table 13.5 register settings in reset synchronous pwm mode........................................... 240 table 13.6 output pins in complementary pwm mode........................................................ 244 table 13.7 register settings in complementary pwm mode................................................ 244 table 13.8 register combinations in buffer operation ......................................................... 254 section 15 14-bit pwm table 15.1 pin configuration.................................................................................................. 282 section 16 serial commun ication interface 3 (sci3) table 16.1 channel configuration.......................................................................................... 286 table 16.2 pin configuration.................................................................................................. 288 table 16.3 examples of brr settings for various bit rates (asynchronous mode) (1) ...... 297 table 16.3 examples of brr settings for various bit rates (asynchronous mode) (2) ...... 298 table 16.3 examples of brr settings for various bit rates (asynchronous mode) (3) ...... 299 table 16.4 maximum bit rate for each frequency (asynchronous mode) .......................... 300 table 16.5 examples of brr settings for various bit rates (clock synchronous mode) (1) ............................................................................ 301 table 16.5 examples of brr settings for various bit rates (clock synchronous mode) (2) ............................................................................ 302
rev. 3.00 sep. 10, 2007 page xxxi of xxxii table 16.6 ssr status flags and receive data handling ...................................................... 308 table 16.7 sci3 interrupt requests........................................................................................ 325 section 17 i 2 c bus interface 2 (iic2) table 17.1 i 2 c bus interface pins ........................................................................................... 331 table 17.2 transfer rate......................................................................................................... 334 table 17.3 interrupt requests ................................................................................................. 362 table 17.4 time for monitoring scl..................................................................................... 363 section 18 a/d converter table 18.1 pin configuration.................................................................................................. 369 table 18.2 analog input channels and corresponding addr registers .............................. 370 table 18.3 a/d conversion time (single mode)................................................................... 375 section 19 band-gap circuit, power-on re set, and low-voltage detection circuits table 19.1 lvdcr settings and select functions ................................................................. 383 table 19.2 deciding reset source.......................................................................................... 392 section 22 electrical characteristics table 22.1 absolute maximum ratings ................................................................................. 415 table 22.2 dc characteristics (1)........................................................................................... 419 table 22.2 dc characteristics (2)........................................................................................... 424 table 22.3 ac characteristics ................................................................................................ 425 table 22.4 i 2 c bus interface timing ...................................................................................... 428 table 22.5 serial communication interface (sci) timing..................................................... 429 table 22.6 a/d converter characteristics .............................................................................. 430 table 22.7 watchdog timer characteristics........................................................................... 431 table 22.8 flash memory characteristics .............................................................................. 432 table 22.9 power-supply-voltage detection circuit characteristics..................................... 434 table 22.10 lvdi external input voltage detection circuit characteristics ...................... 434 table 22.11 power-on reset circuit characteristics............................................................ 435 table 22.12 dc characteristics (1)....................................................................................... 438 table 22.12 dc characteristics (2)....................................................................................... 443 table 22.13 ac characteristics ............................................................................................ 444 table 22.14 i 2 c bus interface timing .................................................................................. 447 table 22.15 serial communication interface (sci) timing ................................................. 448 table 22.16 a/d converter characteristics .......................................................................... 449 table 22.17 watchdog timer characteristics....................................................................... 450 table 22.18 flash memory characteristics .......................................................................... 451 table 22.19 power-supply-voltage detection circuit characteristics................................. 453 table 22.20 lvdi external input voltage detection circuit characteristics ...................... 453 table 22.21 power-on reset circuit characteristics............................................................ 454
rev. 3.00 sep. 10, 2007 page xxxii of xxxii appendix table a.1 instruction set ....................................................................................................... 461 table a.2 operation code map (1) ....................................................................................... 474 table a.2 operation code map (2) ....................................................................................... 475 table a.2 operation code map (3) ....................................................................................... 476 table a.3 number of cycles in each instruction.................................................................. 478 table a.4 number of cycles in each instruction.................................................................. 479 table a.5 combinations of instructions and addressing modes .......................................... 488
section 1 overview rev. 3.00 sep. 10, 2007 page 1 of 528 rej09b0216-0300 section 1 overview 1.1 features ? high-speed h8/300h cpu with an internal 16-bit architecture ? upwardly compatible with h8/300 cpu at the object level ? sixteen 16-bit general registers ? 62 basic instructions ? various peripheral functions ? rtc (can be used as a free running counter) ? timer b1 (8-bit timer) ? timer v (8-bit timer) ? timer z (16-bit timer) ? 14-bit pwm ? watchdog timer ? sci (asynchronous or clock synchronous serial communication interface) 2 channels ? i 2 c bus interface (conforms to the i 2 c bus interface format that is advocated by philips electronics) ? 10-bit a/d converter ? por/lvd (power-on reset & low-voltage detection circuit) ? on-chip oscillator
section 1 overview rev. 3.00 sep. 10, 2007 page 2 of 528 rej09b0216-0300 ? on-chip memory product classification product model rom size ram size remarks 5.0-v model h8/36079gf hd64f36079g 3.3-v model h8/36079lf hd64f36079l 128 kbytes 5.0-v model h8/36078gf hd64f36078g h8/36079 group 3.3-v model h8/36078lf hd64f36078l 96 kbytes 6 kbytes 5.0-v model h8/36077gf hd64f36077g 3.3-v model h8/36077lf hd64f36077l 56 kbytes 5.0-v model h8/36074gf HD64F36074G flash memory version (f-ztat tm version) h8/36077 group 3.3-v model h8/36074lf hd64f36074l 32 kbytes 4 kbytes ? operating voltage and maximum operating frequency product classification product model operating voltage range maximum operating frequency remarks 5.0-v model h8/36079gf hd64f36079g 4.5 v to 5.5 v 20.0 mhz 3.3-v model h8/36079lf hd64f36079l 3.0 v to 3.6 v 16.0 mhz 5.0-v model h8/36078gf hd64f36078g 4.5 v to 5.5 v 20.0 mhz h8/36079 group 3.3-v model h8/36078lf hd64f36078l 3.0 v to 3.6 v 16.0 mhz 5.0-v model h8/36077gf hd64f36077g 4.5 v to 5.5 v 20.0 mhz 3.3-v model h8/36077lf hd64f36077l 3.0 v to 3.6 v 16.0 mhz 5.0-v model h8/36074gf HD64F36074G 4.5 v to 5.5 v 20.0 mhz flash memory version (f-ztat tm version) h8/36077 group 3.3-v model h8/36074lf hd64f36074l 3.0 v to 3.6 v 16.0 mhz
section 1 overview rev. 3.00 sep. 10, 2007 page 3 of 528 rej09b0216-0300 ? cpu operating mode and address space product classification product model address space cpu operating mode remarks 5.0-v model h8/36079gf hd64f36079g 3.3-v model h8/36079lf hd64f36079l 5.0-v model h8/36078gf hd64f36078g h8/36079 group 3.3-v model h8/36078lf hd64f36078l 16 mbytes advanced mode 5.0-v model h8/36077gf hd64f36077g 3.3-v model h8/36077lf hd64f36077l 5.0-v model h8/36074gf HD64F36074G flash memory version (f-ztat tm version) h8/36077 group 3.3-v model h8/36074lf hd64f36074l 64 kbytes normal mode ? general i/o ports ? i/o pins: 47 i/o pins, including 8 for large currents (i ol = 20 ma, @v ol = 1.5 v) ? input-only pins: 8 (also used for analog input) ? i 2 c bus interface (conforms to the i 2 c bus interface format put forward by philips electronics) ? supports various power-down modes note: f-ztat tm is a trademark of renesas technology corp. ? compact package package code body size pin pitch lqfp-64 fp-64k 10.0 10.0 mm 0.5 mm qfp-64 fp-64a 14.0 14.0 mm 0.8 mm
section 1 overview rev. 3.00 sep. 10, 2007 page 4 of 528 rej09b0216-0300 1.2 block diagram p10/tmow p11/pwm p12 p14/ irq0 p15/ irq1 /tmib1 p16/ irq2 p17/ irq3 /trgv p57/scl p56/sda p55/ wkp5 / adtrg p54/ wkp4 p53/ wkp3 p52/ wkp2 p51/ wkp1 p50/ wkp0 pb0/an0 pb1/an1 pb2/an2 pb3/an3 pb4/an4 pb5/an5 pb6/an6/extd pb7/an7/extu v cl v cc v ss res test nmi av cc p20/sck3 p21/rxd p22/txd p23 p24 p87 p86 p85 (osc1) (osc2) x1 x2 cpu h8/300h rom ram data bus (lower) data bus (upper) rtc 14-bit pwm timer z sci3 iic2 sci3_2 timer v timer b1 por&lvd watchdog timer a/d converter p67/ftiod1 p66/ftioc1 p65/ftiob1 p64/ftioa1 p63/ftiod0 p62/ftioc0 p61/ftiob0 p60/ftioa0 p76/tmov p75/tmciv p74/tmriv p72/txd_2 p71/rxd_2 p70/sck3_2 p30 p31 p32 p33 p34 p35 p36 p37 subclock oscillator external clock oscillator on-chip oscillator port b pc0/osc1 pc1/osc2/clkout port c address bus port 3 port 5 port 2 port 1 port 6 port 7 port 8 figure 1.1 block diagram of h8/36079 group and h8/36077 group
section 1 overview rev. 3.00 sep. 10, 2007 page 5 of 528 rej09b0216-0300 1.3 pin arrangement pb6/an6/extd pb7/an7/extu avcc x2 x1 v cl res test vss pc1/osc2/clkout pc0/osc1 vcc p50/ wkp0 p51/ wkp1 p34 p35 1 2 3 4 5 6 7 8 9 10111213141516 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p70/sck3_2 p23 p22/txd p21/rxd p20/sck3 p87 p86 p85 p67/ftiod1 p66/ftioc1 p65/ftiob1 p64/ftioa1 p60/ftioa0 nmi p61/ftiob0 p62/ftioc0 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 p71/rxd_2 p72/txd_2 p14/ irq0 p15/ irq1 /tmib1 p16/ irq2 p17/ irq3 /trgv p33 p32 p31 p30 pb3/an3 pb2/an2 pb1/an1 pb0/an0 pb4/an4 pb5/an5 p63/ftiod0 p24 p76/tmov p75/tmciv p74/tmriv p57/scl p56/sda p12 p11/pwm p10/tmow p55/ wkp5 / adtr g p54/ wkp4 p53/ wkp3 p52/ wkp2 p37 p36 h8/36079 group h8/36077 group top view figure 1.2 pin arrangement of h8/36079 group and h8/36077 group (fp-64k, fp-64a)
section 1 overview rev. 3.00 sep. 10, 2007 page 6 of 528 rej09b0216-0300 1.4 pin functions table 1.1 pin functions pin no. type symbol fp-64k fp-64a i/o functions power source pins v cc 12 input power supply pin. connect this pin to the system power supply. v ss 9 input ground pin. connect this pin to the system power supply (0v). av cc 3 input analog power supply pin for the a/d converter. when the a/d converter is not used, connect this pin to the system power supply. v cl 6 input see section 20, power supply circuit, for a typical connection. clock pins osc1 11 input osc2/ clkout 10 output these pins connect with crystal or ceramic resonator for the system clock, or can be used to input an external clock. when the on-chip oscillator is used, the system clock can be output on osc2 pin. see section 5, clock pulse generator, for a typical connection. x1 5 input x2 4 output these pins connect with a 32.768 khz crystal resonator for the subclock. see section 5, clock pulse generator, for a typical connection. system control res 7 input reset pin. the pull-up resistor (typ. 150 k ? ) is incorporated. when driven low, this lsi is reset. test 8 input test pin. connect this pin to vss. interrupt pins nmi 35 input non-maskable interrupt request input pin. be sure to pull up by a resistor. irq0 to irq3 51 to 54 input external interrupt request input pins. can select the rising or falling edge. wkp0 to wkp5 13, 14, 19 to 22 input external interrupt request input pins. can select the rising or falling edge. rtc tmow 23 output this is an output pin for a divided clock. timer b1 tmib1 52 input external event input pin
section 1 overview rev. 3.00 sep. 10, 2007 page 7 of 528 rej09b0216-0300 pin no. type symbol fp-64k fp-64a i/o functions timer v tmov 30 output this is an output pin for a waveform generated by the output compare function. tmciv 29 input external event input pin tmriv 28 input counter reset input pin trgv 54 input counter start trigger input pin timer z ftioa0 36 i/o output compare output/input capture input/external clock input pin ftiob0 34 i/o output compare output/input capture input/pwm output pin ftioc0 33 i/o output compare output/input capture input/pwm sync output pin (at a reset, complementary pwm mode) ftiod0 32 i/o output compare output/input capture input/pwm output pin ftioa1 37 i/o output compare output/input capture input/pwm output pin (at a reset, complementary pwm mode) ftiob1 to ftiod1 38 to 40 i/o output compare output/input capture input/pwm output pin 14-bit pwm pwm 24 output 14-bit pwm square wave output pin i 2 c bus interface 2 (iic2) sda 26 i/o i 2 c data i/o pin. can directly drive a bus by nmos open-drain output. when using this pin, external pull-up resistor is required. scl 27 i/o i 2 c clock i/o pin. can directly drive a bus by nmos open-drain output. when using this pin, external pull-up resistor is required. txd, txd_2 46, 50 output transmit data output pin serial com- munication interface 3 (sci3) rxd, rxd_2 45, 49 input receive data input pin sck3, sck3_2 44, 48 i/o clock i/o pin
section 1 overview rev. 3.00 sep. 10, 2007 page 8 of 528 rej09b0216-0300 pin no. type symbol fp-64k fp-64a i/o functions a/d converter an7 to an0 2, 1 64, 63 59 to 62 input analog input pin adtrg 22 input a/d conversion start trigger input pin i/o ports pb7 to pb0 2, 1 64, 63 59 to 62 input 8-bit input port pc1, pc0 10, 11 i/o 2-bit i/o port p17 to p14, p12 to p10 54 to 51, 25 to 23 i/o 7-bit i/o port p24 to p20 31, 47 to 44 i/o 5-bit i/o port p37 to p30 18 to 15, 55 to 58 i/o 8-bit i/o port p57 to p50 27, 26 22 to 19 14, 13 i/o 8-bit i/o port p67 to p60 40 to 37 32 to 34, 36 i/o 8-bit i/o port p76 to p74, p72 to p70 30 to 28, 50 to 48 i/o 6-bit i/o port p87 to p85 43 to 41 i/o 3-bit i/o port low-voltage detection circuit extu, extd 2, 1 input this pin is used to externally input the detection voltage for the low-voltage detection circuit.
section 2 cpu cpu30h2c_000120030300 rev. 3.00 sep. 10, 2007 page 9 of 528 rej09b0216-0300 section 2 cpu microcontrollers of the h8/36079 group and h8/36077 group have an h8/300h cpu with an internal 32-bit architecture that provides upward compatibility with the h8/300cpu. products of the h8/36079 group support an advanced mode w ith a 16-mbyte address space while those of the h8/36077 group support a normal mode with a 64-kbyte address space. ? upward compatibility with h8/300 cpus ? can execute object programs for h8/300 cpus ? additional eight 16-bit extended registers ? 32-bit transfer and arithmetic and logic instructions are added ? signed multiply and divide instructions are added. ? general-register architecture ? sixteen 16-bit general registers also usable as sixteen 8-bit registers and eight 16-bit registers, or eight 32-bit registers ? sixty-two basic instructions ? 8/16/32-bit data transfer and arithmetic and logic instructions ? multiply and divide instructions ? powerful bit-manipulation instructions ? eight addressing modes ? register direct [rn] ? register indirect [@ern] ? register indirect with displacemen t [@(d:16,ern) or @(d:24,ern)] ? register indirect with post-increment or pre-decrement [@ern+ or @?ern] ? absolute address [@aa:8, @aa:16, @aa:24] ? immediate [#xx:8, #xx:16, or #xx:32] ? program-counter relative [@(d:8,pc) or @(d:16,pc)] ? memory indirect [@@aa:8] ? address space ? h8/36079 group: 16 mbytes ? h8/36077 group: 64 kbytes
section 2 cpu rev. 3.00 sep. 10, 2007 page 10 of 528 rej09b0216-0300 ? high-speed operation ? all frequently-used instructions execute in one or two states ? 8/16/32-bit register-register add/subtract: 2 state ? 8 8-bit register-register multiply: 14 states ? 16 8-bit register-register divide: 14 states ? 16 16-bit register-register multiply: 22 states ? 32 16-bit register-register divide: 22 states ? cpu operating mode ? h8/36079 group: advanced mode ? h8/36077 group: normal mode ? power-down state ? transition to power-down state by sleep instruction
section 2 cpu rev. 3.00 sep. 10, 2007 page 11 of 528 rej09b0216-0300 2.1 address space and memory map figure 2.1 shows the memory map of the address space of h8/36079 group and h8/36077 group. interrupt vector on-chip rom (128 kbytes) not used (1-kbyte working area for flash memory programming) on-chip emulator firmware area (4 kbytes) internal i/o register h'000000 h'00008b h'00008c h'01ffff h'fffb7f h'ffff7f h'ffff80 h'fffb80 h'fff77f h'fff780 h'fff700 h'ffefff h'ffe000 h'ffffff hd64f36079g hd64f36079l (flash memory version) h'01f000 h'01efff h'000000 h'00008b h'00008c h'017fff h'fffb7f h'ffff7f h'ffff80 h'fffb80 h'fff77f h'fff780 h'fff700 h'ffefff h'ffe000 h'ffffff internal i/o register not used on-chip ram (4 kbytes) (1-kbyte user area) on-chip ram (2 kbytes) interrupt vector on-chip rom (96 kbytes) (1-kbyte working area for flash memory programming) internal i/o register hd64f36078g hd64f36078l (flash memory version) internal i/o register not used not used on-chip ram (4 kbytes) (1-kbyte user area) on-chip ram (2 kbytes) interrupt vector on-chip rom (56 kbytes) not used (1-kbyte working area for flash memory programming) on-chip emulator firmware area (4 kbytes) internal i/o register h'0000 h'0045 h'0046 h'dfff h'fb7f h'ff7f h'ff80 h'fb80 h'f77f h'f780 h'f700 h'efff h'e800 h'ffff hd64f36077g hd64f36077l (flash memory version) h'd000 h'cfff internal i/o register not used on-chip ram (2 kbytes) (1-kbyte user area) on-chip ram (2 kbytes) interrupt vector on-chip rom (32 kbytes) not used (1-kbyte working area for flash memory programming) internal i/o register h'0000 h'0045 h'0046 h'7fff h'fb7f h'ff7f h'ff80 h'fb80 h'f77f h'f780 h'f700 h'efff h'e800 h'ffff HD64F36074G hd64f36074l (flash memory version) internal i/o register not used on-chip ram (2 kbytes) (1-kbyte user area) on-chip ram (2 kbytes) figure 2.1 memory map
section 2 cpu rev. 3.00 sep. 10, 2007 page 12 of 528 rej09b0216-0300 2.2 register configuration the h8/300h cpu has the internal registers shown in figure 2.2. there are two types of registers; general registers and control registers. the control registers are a 24-bit program counter (pc), and an 8-bit condition-code register (ccr). pc 23 0 15 0 7 0 7 0 e0 e1 e2 e3 e4 e5 e6 e7 r0h r1h r2h r3h r4h r5h r6h r7h r0l r1l r2l r3l r4l r5l r6l r7l sp: pc: ccr: i: ui: stack pointer program counter condition-code register interrupt mask bit user bit half-carry flag user bit negative flag zero flag overflow flag carry flag er0 er1 er2 er3 er4 er5 er6 er7 iuihunzvc ccr 76543210 h: u: n: z: v: c: general registers (ern) control registers (cr) [legend] (sp) figure 2.2 cpu registers
section 2 cpu rev. 3.00 sep. 10, 2007 page 13 of 528 rej09b0216-0300 2.2.1 general registers the h8/300h cpu has eight 32-bit general registers. these general registers are all functionally identical and can be used as both address regist ers and data registers. the general registers are available for use as 32-, 16-, and 8-bit data registers. figure 2.3 illustrates the usage of the general registers. when the general registers are used as 32-bit registers or address registers, they are designated by the letters er (er0 to er7). the er registers are divided into 16-bit general registers designated by the letters e (e0 to e7) and r (r0 to r7). these registers are functionally equivalent, providing a maximum of sixteen 16- bit registers. the e registers (e0 to e7) ar e also referred to as extended registers. the r registers are divided into 8-bit registers designated by the letters rh (r0h to r7h) and rl (r0l to r7l). these registers are functionally equivalent, providing a maximum of sixteen 8-bit registers. the usage of each register can be selected independently. address registers 32-bit registers 16-bit registers 8-bit registers er registers (er0 to er7) e registers (extended registers) (e0 to e7) r registers (r0 to r7) rh registers (r0h to r7h) rl registers (r0l to r7l) figure 2.3 usage of general registers general register er7 has the function of stack poi nter (sp) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. figure 2.4 shows the relationship between the stack pointer and the stack area.
section 2 cpu rev. 3.00 sep. 10, 2007 page 14 of 528 rej09b0216-0300 sp (er7) empty area stack area figure 2.4 relationship between stack pointer and stack area 2.2.2 program counter (pc) this 24-bit counter indicates the address of the next instruction the cpu will execute. the length of all cpu instructions is 2 bytes (one word), so the least significant pc bit is ignored. (when an instruction is fetched, the least significant pc bit is regarded as 0). the pc is initialized when the start address is loaded by the vector address ge nerated during reset exception-handling sequence. 2.2.3 condition-code register (ccr) this 8-bit register contains internal cpu status information, including an interrupt mask bit (i) and half-carry (h), negative (n), zero (z), overflow (v), and carry (c) flags. the i bit is initialized to 1 by reset exception-handling sequence, but other bits are not initialized. some instructions leave flag bits unchanged. operations can be performed on the ccr bits by the ldc, stc, andc, orc, and xorc instructions. the n, z, v, and c flags are used as branching conditions for conditional branch (bcc) instructions. for the action of each instruction on the flag bits, see appendix a.1, instruction list.
section 2 cpu rev. 3.00 sep. 10, 2007 page 15 of 528 rej09b0216-0300 bit bit name initial value r/w description 7 i 1 r/w interrupt mask bit masks interrupts other than nmi when set to 1. nmi is accepted regardless of the i bit setting. the i bit is set to 1 at the start of an exception-handling sequence. 6 ui undefined r/w user bit can be written and read by software using the ldc, stc, andc, orc, and xorc instructions. 5 h undefined r/w half-carry flag when the add.b, addx.b, sub.b, subx.b, cmp.b, or neg.b instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. when the add.w, sub.w, cmp.w, or neg.w instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. when the add.l, sub.l, cmp.l, or neg.l instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. 4 u undefined r/w user bit can be written and read by software using the ldc, stc, andc, orc, and xorc instructions. 3 n undefined r/w negative flag stores the value of the most significant bit of data as a sign bit. 2 z undefined r/w zero flag set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. 1 v undefined r/w overflow flag set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. 0 c undefined r/w carry flag set to 1 when a carry occurs, and cleared to 0 otherwise. used by: ? add instructions, to indicate a carry ? subtract instructions, to indicate a borrow ? shift and rotate instructions, to indicate a carry the carry flag is also used as a bit accumulator by bit manipulation instructions.
section 2 cpu rev. 3.00 sep. 10, 2007 page 16 of 528 rej09b0216-0300 2.3 data formats the h8/300h cpu can process 1-bit, 4-bit (bcd), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. bit-manipul ation instructions operate on 1-bit da ta by accessing bit n (n = 0, 1, 2, ?, 7) of byte operand data. the daa and das decimal-adjust instructions treat byte data as two digits of 4-bit bcd data. 2.3.1 general register data formats figure 2.5 shows the data formats in general registers. 7 0 7 0 msb lsb msb lsb 70 4 3 don't care don't care don't care 7 0 4 3 70 don't care 65432 71 0 7 0 don't care 65432 710 don't care rnh rnl rnh rnl rnh rnl data type general register data format byte data byte data 4-bit bcd data 4-bit bcd data 1-bit data 1-bit data upper lower upper lower figure 2.5 general re gister data formats (1)
section 2 cpu rev. 3.00 sep. 10, 2007 page 17 of 528 rej09b0216-0300 15 0 msb lsb 15 0 msb lsb 31 16 msb 15 0 lsb ern: en: rn: rnh: rnl: msb: lsb: general register er general register e general register r general register rh general register rl most significant bit least significant bit data type data format general register word data word data rn en longword data [legend] ern figure 2.5 general re gister data formats (2)
section 2 cpu rev. 3.00 sep. 10, 2007 page 18 of 528 rej09b0216-0300 2.3.2 memory data formats figure 2.6 shows the data formats in memory . the h8/300h cpu can access word data and longword data in memory, however word or longword data must begin at an even address. if an attempt is made to access word or longword data at an odd address, an address error does not occur, however the least significan t bit of the address is regarded as 0, so access begins the preceding address. this also a pplies to instruction fetches. when er7 (sp) is used as an address register to access the stack area, the operand size should be word or longword. 70 76 543210 msb lsb msb msb lsb lsb data type address 1-bit data byte data word data address l address l address 2m address 2m+1 longword data address 2n address 2n+1 address 2n+2 address 2n+3 data format figure 2.6 memory data formats
section 2 cpu rev. 3.00 sep. 10, 2007 page 19 of 528 rej09b0216-0300 2.4 instruction set 2.4.1 table of instructions classified by function the h8/300h cpu has 62 instructions. tables 2.2 to 2.9 summarize the instructions in each functional category. the notation used in tables 2.2 to 2.9 is defined below. table 2.1 operation notation symbol description rd general register (destination) * rs general register (source) * rn general register * ern general register (32-bit register or address register) (ead) destination operand (eas) source operand ccr condition-code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr pc program counter sp stack pointer #imm immediate data disp displacement + addition ? subtraction multiplication division logical and logical or logical xor move not (logical complement) :3/:8/:16/:24 3-, 8-, 16-, or 24-bit length
section 2 cpu rev. 3.00 sep. 10, 2007 page 20 of 528 rej09b0216-0300 note: * general registers include 8-bit registers (r0h to r7h, r0l to r7l), 16-bit registers (r0 to r7, e0 to e7), and 32-bit registers/address register (er0 to er7). table 2.2 data transfer instructions instruction size * function mov b/w/l (eas) rd, rs (ead) moves data between two general registers or between a general register and memory, or moves immediate data to a general register. movfpe b (eas) rd cannot be used in this lsi. movtpe b rs (eas) cannot be used in this lsi. pop w/l @sp+ rn pops a general register from the stack. pop.w rn is identical to mov.w @sp+, rn. pop.l ern is identical to mov.l @sp+, ern. push w/l rn @?sp pushes a general register onto the stack. push.w rn is identical to mov.w rn, @?sp. push.l ern is identical to mov.l ern, @?sp. note: * refers to the operand size. b: byte w: word l: longword
section 2 cpu rev. 3.00 sep. 10, 2007 page 21 of 528 rej09b0216-0300 table 2.3 arithmetic operations instructions (1) instruction size * function add sub b/w/l rd rs rd, rd #imm rd performs addition or subtraction on data in two general registers, or on immediate data and data in a general register (immediate byte data cannot be subtracted from byte data in a general register. use the subx or add instruction.) addx subx b rd rs c rd, rd #imm c rd performs addition or subtraction with carry on byte data in two general registers, or on immediate data and data in a general register. inc dec b/w/l rd 1 rd, rd 2 rd increments or decrements a general register by 1 or 2. (byte operands can be incremented or decremented by 1 only.) adds subs l rd 1 rd, rd 2 rd, rd 4 rd adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. daa das b rd (decimal adjust) rd decimal-adjusts an addition or subtracti on result in a general register by referring to the ccr to produce 4-bit bcd data. mulxu b/w rd rs rd performs unsigned multiplication on data in two general registers: either 8 bits 8 bits 16 bits or 16 bits 16 bits 32 bits. mulxs b/w rd rs rd performs signed multiplication on data in two general registers: either 8 bits 8 bits 16 bits or 16 bits 16 bits 32 bits. divxu b/w rd rs rd performs unsigned division on data in two general registers: either 16 bits 8 bits 8-bit quotient and 8-bit remainder or 32 bits 16 bits 16-bit quotient and 16-bit remainder. note: * refers to the operand size. b: byte w: word l: longword
section 2 cpu rev. 3.00 sep. 10, 2007 page 22 of 528 rej09b0216-0300 table 2.3 arithmetic operations instructions (2) instruction size * function divxs b/w rd rs rd performs signed division on data in two general registers: either 16 bits 8 bits 8-bit quotient and 8-bit remainder or 32 bits 16 bits 16-bit quotient and 16-bit remainder. cmp b/w/l rd ? rs, rd ? #imm compares data in a general register with data in another general register or with immediate data, and sets ccr bits according to the result. neg b/w/l 0 ? rd rd takes the two's complement (arithmetic complement) of data in a general register. extu w/l rd (zero extension) rd extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. exts w/l rd (sign extension) rd extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. note: * refers to the operand size. b: byte w: word l: longword
section 2 cpu rev. 3.00 sep. 10, 2007 page 23 of 528 rej09b0216-0300 table 2.4 logic operations instructions instruction size * function and b/w/l rd rs rd, rd #imm rd performs a logical and operation on a general register and another general register or immediate data. or b/w/l rd rs rd, rd #imm rd performs a logical or operation on a general register and another general register or immediate data. xor b/w/l rd rs rd, rd #imm rd performs a logical exclusive or operation on a general register and another general register or immediate data. not b/w/l (rd) (rd) takes the one's complement (logical complement) of general register contents. note: * refers to the operand size. b: byte w: word l: longword table 2.5 shift instructions instruction size * function shal shar b/w/l rd (shift) rd performs an arithmetic shift on general register contents. shll shlr b/w/l rd (shift) rd performs a logical shift on general register contents. rotl rotr b/w/l rd (rotate) rd rotates general register contents. rotxl rotxr b/w/l rd (rotate) rd rotates general register contents through the carry flag. note: * refers to the operand size. b: byte w: word l: longword
section 2 cpu rev. 3.00 sep. 10, 2007 page 24 of 528 rej09b0216-0300 table 2.6 bit manipulation instructions (1) instruction size * function bset b 1 ( of ) sets a specified bit in a general register or memory operand to 1. the bit number is specified by 3-bit immediate data or the lower three bits of a general register. bclr b 0 ( of ) clears a specified bit in a general register or memory operand to 0. the bit number is specified by 3-bit immediate data or the lower three bits of a general register. bnot b ( of ) ( of ) inverts a specified bit in a general register or memory operand. the bit number is specified by 3-bit immediate data or the lower three bits of a general register. btst b ( of ) z tests a specified bit in a general register or memory operand and sets or clears the z flag accordingly. the bit number is specified by 3-bit immediate data or the lower three bits of a general register. band biand b b c ( of ) c ands the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. c ? ( of ) c ands the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. the bit number is specified by 3-bit immediate data. bor bior b b c ( of ) c ors the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. c ( of ) c ors the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. the bit number is specified by 3-bit immediate data. note: * refers to the operand size. b: byte
section 2 cpu rev. 3.00 sep. 10, 2007 page 25 of 528 rej09b0216-0300 table 2.6 bit manipulation instructions (2) instruction size * function bxor bixor b b c ( of ) c xors the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. c ( of ) c xors the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. the bit number is specified by 3-bit immediate data. bld bild b b ( of ) c transfers a specified bit in a general register or memory operand to the carry flag. ( of ) c transfers the inverse of a specified bit in a general register or memory operand to the carry flag. the bit number is specified by 3-bit immediate data. bst bist b b c ( of ) transfers the carry flag value to a specified bit in a general register or memory operand. c ( of ) transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. the bit number is specified by 3-bit immediate data. note: * refers to the operand size. b: byte
section 2 cpu rev. 3.00 sep. 10, 2007 page 26 of 528 rej09b0216-0300 table 2.7 branch instructions instruction size function bcc * ? branches to a specified address if a specified condition is true. the branching conditions are listed below. mnemonic description condition bra(bt) always (true) always brn(bf) never (false) never bhi high c z = 0 bls low or same c z = 1 bcc(bhs) carry clear (high or same) c = 0 bcs(blo) carry set (low) c = 1 bne not equal z = 0 beq equal z = 1 bvc overflow clear v = 0 bvs overflow set v = 1 bpl plus n = 0 bmi minus n = 1 bge greater or equal n v = 0 blt less than n v = 1 bgt greater than z (n v) = 0 ble less or equal z (n v) = 1 jmp ? branches unconditionally to a specified address. bsr ? branches to a subroutine at a specified address. jsr ? branches to a subroutine at a specified address. rts ? returns from a subroutine note: * bcc is the general name for conditional branch instructions.
section 2 cpu rev. 3.00 sep. 10, 2007 page 27 of 528 rej09b0216-0300 table 2.8 system co ntrol instructions instruction size * function trapa ? starts trap-instruction exception handling. rte ? returns from an exception-handling routine. sleep ? causes a transition to a power-down state. ldc b/w (eas) ccr moves the source operand contents to the ccr. the ccr size is one byte, but in transfer from memory, data is read by word access. stc b/w ccr (ead) transfers the ccr contents to a destination location. the condition code register size is one byte, but in transfer to memory, data is written by word access. andc b ccr #imm ccr logically ands the ccr with immediate data. orc b ccr #imm ccr logically ors the ccr with immediate data. xorc b ccr #imm ccr logically xors the ccr with immediate data. nop ? pc + 2 pc only increments the program counter. note: * refers to the operand size. b: byte w: word
section 2 cpu rev. 3.00 sep. 10, 2007 page 28 of 528 rej09b0216-0300 table 2.9 block data transfer instructions instruction size function eepmov.b ? if r4l 0 then repeat @er5+ @er6+, r4l?1 r4l until r4l = 0 else next; eepmov.w ? if r4 0 then repeat @er5+ @er6+, r4?1 r4 until r4 = 0 else next; transfers a data block. starting from the address set in er5, transfers data for the number of bytes set in r4l or r4 to the address location set in er6. execution of the next instruction begins as soon as the transfer is completed.
section 2 cpu rev. 3.00 sep. 10, 2007 page 29 of 528 rej09b0216-0300 2.4.2 basic instruction formats h8/300h cpu instructions consist of 2-byte (1-word) units. an instruction consists of an operation field (op), a register field (r), an effective address extension (ea), and a condition field (cc). figure 2.7 shows examples of instruction formats. ? operation field indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. the operation field always includes the first four bits of the instruction. some instructions have two operation fields. ? register field specifies a general register. address registers ar e specified by 3 bits, and data registers by 3 bits or 4 bits. some instructions have two register fields. some have no register field. ? effective address extension 8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. a24-bit address or displacement is treated as a 32-bit data in which the first 8 bits are 0 (h'00). ? condition field specifies the branching condition of bcc instructions. op op rn rm nop, rts, etc. add.b rn, rm, etc. mov.b @(d:16, rn), rm rn rm op ea(disp) op cc ea(disp) bra d:8 (1) operation field only (2) operation field and register fields (3) operation field, register fields, and effective address extension (4) operation field, effective address extension, and condition field figure 2.7 instruction formats
section 2 cpu rev. 3.00 sep. 10, 2007 page 30 of 528 rej09b0216-0300 2.5 addressing modes and eff ective address calculation 2.5.1 addressing modes the h8/300h cpu supports the eight addressing modes listed in table 2.10. each instruction uses a subset of these addressing modes. addressing modes that can be used differ depending on the instruction. for details, refer to appendix a.4, combinations of instructions and addressing modes. arithmetic and logic instructions can use the regist er direct and immediate modes. data transfer instructions can use all addressing modes except program-counter relative and memory indirect. bit-manipulation instructions use register direct, register indirect, or the absolute addressing mode (@aa:8) to specify an operand, and register direct (bset, bclr, bnot, and btst instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. table 2.10 addressing modes no. addressing mode symbol 1 register direct rn 2 register indirect @ern 3 register indirect with displacement @(d:16,ern)/@(d:24,ern) 4 register indirect with post-increment register indirect with pre-decrement @ern+ @?ern 5 absolute address @aa:8/@aa:16/@aa:24 6 immediate #xx:8/#xx:16/#xx:32 7 program-counter relative @(d:8,pc)/@(d:16,pc) 8 memory indirect @@aa:8 (1) register direct ? the register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. r0h to r7h and r0l to r7l can be specified as 8-bit registers. r0 to r7 and e0 to e7 can be specified as 16-bit registers. er0 to er7 can be specified as 32-bit registers.
section 2 cpu rev. 3.00 sep. 10, 2007 page 31 of 528 rej09b0216-0300 (2) register indirect ? the register field of the instruc tion code specifies an address register (ern), the lower 24 bits of which contain the address of the operand on memory. (3) register indirect with displacement ? a 16-bit or 24-bit displacement contained in the inst ruction is added to an address register (ern) specified by the register fi eld of the instruction, and the lower 24 bits of the sum the address of a memory operand. a 16-bit displacement is sign-extended when added. (4) register indirect with po st-increment or pre-decrement ? ? the register field of the instru ction code specifies an address register (ern) the lower 24 bits of which contains the address of a memory operand. after the operand is accessed, 1, 2, or 4 is added to the address register contents (32 bits) and the sum is stored in the address register. the value added is 1 for byte access, 2 for word access, or 4 for longword access. for the word or longword access, the regist er value should be even. (b) register indirect with pre-decrement ? the value 1, 2, or 4 is subtracted from an address register (ern) specified by the register field in the instruction code, and the lower 24 bits of the result is the address of a memory operand. the result is also stored in the address register . the value subtracted is 1 for byte access, 2 for word access, or 4 for longword access. for the wo rd or longword access, the register value should be even. (5) absolute address ? the instruction code contains th e absolute address of a memory operand. the absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24) for an 8-bit absolute address, the upper 16 bits are all assume d to be 1 (h' ffff). for a 16-bit absolute address the upper 8 bits are a sign ex tension. a 24-bit absolute address can access the entire address space. table 2.11 shows the access ranges of absolute a ddresses according to the modes of operation of each product group.
section 2 cpu rev. 3.00 sep. 10, 2007 page 32 of 528 rej09b0216-0300 table 2.11 absolute address access ranges absolute address normal mode advanced mode 8 bits (@aa:8) h'ff00 to h'ffff h'ffff00 to h'ffffff 16 bits (@aa:16) h'0000 to h'ffff h'000000 to h'007fff h'ff8000 to h'ffffff 24 bits (@aa:24) h'0000 to h'ffff h'000000 to h'ffffff (6) immediate ? the instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. the adds, subs, inc, and dec instructions contain immediate data implicitly. some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. the trapa instruction contains 2-bit immediate data in its instruction code, specifying a vector address. (7) program-counter relative ? this mode is used in the bsr instruction. an 8-bit or 16-b it displacement contained in the instruction is sign-extended and added to the 24-bit pc contents to generate a branch address. the pc value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is ?126 to +128 bytes (?63 to +64 words) or ?32766 to +32768 bytes (?16383 to +16384 words) from the branch instruction. the resulting value should be an even number. (8) memory indirect ? this mode can be used by the jmp and jsr instructions. the instruction code contains an 8-bit absolute address specifying a memory operand. this memory operand contains a branch address. the memory operand is accessed by longword acce ss. the first byte of the memory operand is ignored, generating a 24-bit branch address. figure 2.8 shows how to specify branch address for in memory indirect mode. the upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (h'0000 to h'00ff). note that the first part of the address range is also the exception vector area.
section 2 cpu rev. 3.00 sep. 10, 2007 page 33 of 528 rej09b0216-0300 specified by @aa:8 branch address dummy figure 2.8 branch a ddress specification in memory indirect mode 2.5.2 effective address calculation table 2.12 indicates how effe ctive addresses are calculated in each addressing mode. for operation in normal mode, the upper 8 bits of the ef fective address are ignored in order to generate a 16-bit effective address. for operation in advanced mode, the 24-bit result of effective address calculation is generated as the address.
section 2 cpu rev. 3.00 sep. 10, 2007 page 34 of 528 rej09b0216-0300 table 2.12 effective a ddress calculation (1) no 1 r o p 31 0 23 2 3 registe r indi rect with dis placement @(d: 16,ern) or @(d: 24,ern) 4 r o p dis p r op rm op rn 3 1 0 0 r o p 2 3 0 31 0 disp 31 0 31 0 23 0 23 0 addressing mode and instruction format effective address calculation effective address (ea) register direct(rn) general register contents general register contents general register contents general register contents sign extension register indirect(@ern) register indirect with post-increment or pre-decrement register indirect with post-increment @ern+ register indirect with pre-decrement @-ern 1, 2, or 4 1, 2, or 4 operand is general register contents. the value to be added or subtracted is 1 when the operand is byte size, 2 for word size, and 4 for longword size.
section 2 cpu rev. 3.00 sep. 10, 2007 page 35 of 528 rej09b0216-0300 table 2.12 effective a ddress calculation (2) no 5 op 23 0 abs @aa:8 7 h'ffff op 23 0 @aa:16 @aa :24 abs 15 16 23 0 o p abs 6 o p imm #xx :8 /#xx :16 /#xx :32 8 addressing mode and instruction format absolute address immediate effective address calculation effective address (ea) sign extension operand is immediate data. 7 p rogr am- counter re lativ e @ (d:8 ,pc ) @( d:16 ,pc) m em ory indirect @@aa :8 23 0 dis p 0 23 0 dis p op 23 op 8 abs 23 0 abs h'0000 7 8 0 1 5 23 0 1 5 h'00 16 [legend] r, rm,rn : op : disp : imm : abs : register field operation field displacement immediate data absolute address pc contents sign extension memory contents
section 2 cpu rev. 3.00 sep. 10, 2007 page 36 of 528 rej09b0216-0300 2.6 basic bus cycle cpu operation is synchronized by a system clock ( ) or a subclock ( sub ). the period from a rising edge of or sub to the next rising edge is called one state. a bus cycle consists of two states or three states. the cycle differs depending on whet her access is to on-chip memory or to on-chip peripheral modules. 2.6.1 access to on-chip memory (ram, rom) access to on-chip memory takes place in two stat es. the data bus width is 16 bits, allowing access in byte or word size. figure 2.9 s hows the on-chip memory access cycle. t 1 state bus cycle t 2 state internal address bus internal read signal internal data bus (read access) internal write signal read data address write data internal data bus (write access) sub ? or ? figure 2.9 on-chip memory access cycle
section 2 cpu rev. 3.00 sep. 10, 2007 page 37 of 528 rej09b0216-0300 2.6.2 on-chip peripheral modules on-chip peripheral modules are accessed in two states or three states. the data bus width is 8 bits or 16 bits depending on the register. for description on the data bus width and number of accessing states of each register, refer to sec tion 21.1, register addresses (address order). registers with 16-bit data bus width can be accesse d by word size only. registers with 8-bit data bus width can be accessed by byte or word size. wh en a register with 8-bit data bus width is accessed by word size, a bus cycle occurs twice. in two-state access, the operation timing is the same as that for on-chip memory. figure 2.10 shows the operation timing in the cas e of three-state access to an on-chip peripheral module. t 1 state bus cycle internal address bus internal read signal internal data bus (read access) internal write signal read data address internal data bus (write access) t 2 state t 3 state write data sub or figure 2.10 on-chip peripheral mo dule access cycle (3-state access)
section 2 cpu rev. 3.00 sep. 10, 2007 page 38 of 528 rej09b0216-0300 2.7 cpu states there are four cpu states: the reset state, pr ogram execution state, program halt state, and exception-handling state. the program execution st ate includes active mode and subactive mode. for the program halt state, there are a sleep mode, standby mode, and sub-sleep mode. these states are shown in figure 2.11. figure 2.12 shows the state transitions. for details on program execution state and program halt state, refer to section 6, power-down modes. for details on exception processing, refer to section 3, exception handling. cpu state reset state program execution state program halt state exception- handling state active (high speed) mode subactive mode sleep mode subsleep mode power-down modes the cpu executes successive program instructions at high speed, synchronized by the system clock the cpu executes successive program instructions at reduced speed, synchronized by the subclock a state in which some or all of the chip functions are stopped to conserve power a transient state in which the cpu changes the processing flow due to a reset or an interrupt the cpu is initialized standby mode figure 2.11 cpu operation states
section 2 cpu rev. 3.00 sep. 10, 2007 page 39 of 528 rej09b0216-0300 reset state program halt state exception-handling state program execution state reset cleared sleep instruction executed reset occurs interrupt source reset occurs interrupt source exception- handling complete reset occurs figure 2.12 state transitions 2.8 usage notes 2.8.1 notes on data access to empty areas the address space of this lsi includes empty areas in addition to the rom, ram, and on-chip i/o registers areas available to the user. when da ta is transferred from cpu to empty areas, the transferred data will be lost. this action may also cause the cpu to malfunction. when data is transferred from an empty area to cpu, the contents of the data cannot be guaranteed. 2.8.2 eepmov instruction eepmov is a block-transfer instruction and tran sfers the number of bytes indicated by r4l and starting at the address indicated by r5 to the address indicated by r6. in products for normal- mode operation, set r4l and r6 so that the final address at the destination for transfer (value of r6 + r4l) does not exceed h'ffff (t he value of r6 must no t change from h'ffff to h'0000 during execution). in products for advanced-mode operation, set r4l and r6 so that the final address at the destination for transfer (value of r6 + r4l) does not exceed h'ffffff (the value of r6 must not change from h'ffffff to h'000000 during execution).
section 2 cpu rev. 3.00 sep. 10, 2007 page 40 of 528 rej09b0216-0300 2.8.3 bit-manipulation instruction the bset, bclr, bnot, bst, and bist instructi ons read data from the specified address in byte units, manipulate the data of the target bit, and write data to the same address again in byte units. special care is required when using these instructions in cases where two registers are assigned to the same address, or when a bit is directly manipulated for a port or a register containing a write-only bit, because this may rewrite data of a bit other than the bit to be manipulated. (1) bit manipulation for two registers assigned to the same address example 1: bit manipulation for the timer load register and timer counter (applicable for timer b1 in the h8/36079 group and h8/36077 group.) figure 2.13 shows an example of a timer in which two timer registers are assigned to the same address. when a bit-manipulation instruction accesses the timer load register and timer counter of a reloadable timer, since these two registers share the same address, the following operations takes place. 1. data is read in byte units. 2. the cpu sets or resets the bit to be manipulated with the bit-manipulation instruction. 3. the written data is written again in byte units to the timer load register. the timer is counting, so the value read is not necessarily the same as the value in the timer load register. as a result, bits other than the intended bit in the timer counter may be modified and the modified value may be written to the timer load register. read write count clock timer counter timer load register reload internal data bus figure 2.13 example of timer configuration with two registers allocated to same address
section 2 cpu rev. 3.00 sep. 10, 2007 page 41 of 528 rej09b0216-0300 example 2: the bset instruct ion is executed for port 5. p57 and p56 are input pins, with a low-level signal input at p57 and a high-level signal input at p56. p55 to p50 are output pins and output low-level signals. an example to output a high-level signal at p50 with a bset instruction is shown below. ? prior to executing bset instruction p57 p56 p55 p54 p53 p52 p51 p50 input/output input input output output output output output output pin state low level high level low level low level low level low level low level low level pcr5 0 0 1 1 1 1 1 1 pdr5 1 0 0 0 0 0 0 0 ? bset instruction executed instruction bset #0, @pdr5 the bset instruction is executed for port 5. ? after executing bset instruction p57 p56 p55 p54 p53 p52 p51 p50 input/output input input output output output output output output pin state low level high level low level low level low level low level low level high level pcr5 0 0 1 1 1 1 1 1 pdr5 0 1 0 0 0 0 0 1 ? description on operation 1. when the bset instruction is executed, first the cpu reads port 5. since p57 and p56 are input pins, the cpu reads the pin states (low-level and high-level input). p55 to p50 are output pins, so the cpu reads the value in pdr5. in this example pdr5 has a value of h'80, but the value read by the cpu is h'40. 2. next, the cpu sets bit 0 of the read data to 1, changing the pdr5 data to h'41. 3. finally, the cpu writes h'41 to pdr5, completing execution of bset instruction.
section 2 cpu rev. 3.00 sep. 10, 2007 page 42 of 528 rej09b0216-0300 as a result of the bset instruction, bit 0 in pdr5 becomes 1, and p50 outputs a high-level signal. however, bits 7 and 6 of pdr5 end up with different values. to prevent this problem, store a copy of the pdr5 data in a work area in memory. perform the bit manipulation on the data in the work area, then write this data to pdr5. ? prior to executing bset instruction mov.b #80, r0l mov.b r0l, @ram0 mov.b r0l, @pdr5 the pdr5 value (h'80) is written to a work area in memory (ram0) as well as to pdr5. p57 p56 p55 p54 p53 p52 p51 p50 input/output input input output output output output output output pin state low level high level low level low level low level low level low level low level pcr5 0 0 1 1 1 1 1 1 pdr5 1 0 0 0 0 0 0 0 ram0 1 0 0 0 0 0 0 0 ? bset instruction executed bset #0, @ram0 the bset instruction is executed designating the pdr5 work area (ram0). ? after executing bset instruction mov.b @ram0, r0l mov.b r0l, @pdr5 the work area (ram0) value is written to pdr5. p57 p56 p55 p54 p53 p52 p51 p50 input/output input input output output output output output output pin state low level high level low level low level low level low level low level high level pcr5 0 0 1 1 1 1 1 1 pdr5 1 0 0 0 0 0 0 1 ram0 1 0 0 0 0 0 0 1
section 2 cpu rev. 3.00 sep. 10, 2007 page 43 of 528 rej09b0216-0300 (2) bit manipulation in a regist er containing a write-only bit example 3: bclr instruction executed de signating port 5 co ntrol register pcr5 p57 and p56 are input pins, with a low-level signal input at p57 and a high-level signal input at p56. p55 to p50 are output pins that output low-level signals. an example of setting the p50 pin as an input pin by the bclr instruc tion is shown below. it is assume d that a high-level signal will be input to this input pin. ? prior to executing bclr instruction p57 p56 p55 p54 p53 p52 p51 p50 input/output input input output output output output output output pin state low level high level low level low level low level low level low level low level pcr5 0 0 1 1 1 1 1 1 pdr5 1 0 0 0 0 0 0 0 ? bclr instruction executed bclr #0, @pcr5 the bclr instruction is executed for pcr5. ? after executing bclr instruction p57 p56 p55 p54 p53 p52 p51 p50 input/output output output output output output output output input pin state low level high level low level low level low level low level low level high level pcr5 1 1 1 1 1 1 1 0 pdr5 1 0 0 0 0 0 0 0 ? description on operation 1. when the bclr instruction is executed, firs t the cpu reads pcr5. since pcr5 is a write-only register, the cpu reads a value of h'ff, ev en though the pcr5 value is actually h'3f. 2. next, the cpu clears bit 0 in the read data to 0, changing the data to h'fe. 3. finally, h'fe is written to pcr5 and bclr instruction execution ends. as a result of this operation, bit 0 in pcr5 becomes 0, making p50 an input port. however, bits 7 and 6 in pcr5 change to 1, so that p57 and p56 change from input pins to output pins. to prevent this problem, store a copy of the pdr5 data in a work area in memory and manipulate data of the bit in the work area, then write this data to pdr5.
section 2 cpu rev. 3.00 sep. 10, 2007 page 44 of 528 rej09b0216-0300 ? prior to executing bclr instruction mov.b #3f, r0l mov.b r0l, @ram0 mov.b r0l, @pcr5 the pcr5 value (h'3f) is written to a work area in memory (ram0) as well as to pcr5. p57 p56 p55 p54 p53 p52 p51 p50 input/output input input output output output output output output pin state low level high level low level low level low level low level low level low level pcr5 0 0 1 1 1 1 1 1 pdr5 1 0 0 0 0 0 0 0 ram0 0 0 1 1 1 1 1 1 ? bclr instruction executed bclr #0, @ram0 the bclr instructions execute d for the pcr5 work area (ram0). ? after executing bclr instruction mov.b @ram0, r0l mov.b r0l, @pcr5 the work area (ram0) value is written to pcr5. p57 p56 p55 p54 p53 p52 p51 p50 input/output input input output output output output output output pin state low level high level low level low level low level low level low level high level pcr5 0 0 1 1 1 1 1 0 pdr5 1 0 0 0 0 0 0 0 ram0 0 0 1 1 1 1 1 0
section 3 exception handling rev. 3.00 sep. 10, 2007 page 45 of 528 rej09b0216-0300 section 3 exception handling exception handling may be caused by a reset, a trap instruction (trapa), or interrupts. ? reset a reset has the highest exception priority. exception handling starts as soon as the reset is cleared by the res pin. the chip is also reset when the watchdog timer overflows, and exception handling starts. exception handling is the same as exception handling by the res pin. ? trap instruction exception handling starts when a trap instruction (trapa ) is executed. the trapa instruction generates a vector address corresponding to a vector number from 0 to 3, as specified in the instruction code. exception handling can be executed at all times in the program execution state, regardless of the setting of the i bit in ccr. ? interrupts external interrupts other than nmi and internal interrupts other than address break are masked by the i bit in ccr, and kept masked while the i bit is set to 1. exception handling starts when the current instruction or exception handling ends, if an interrupt request has been issued.
section 3 exception handling rev. 3.00 sep. 10, 2007 page 46 of 528 rej09b0216-0300 3.1 exception sources and vector address table 3.1 shows the vector addresses and priority of each exception handling. when more than one interrupt is requested, handling is performed from the interrupt with the highest priority. table 3.1 exception sources and vector address relative module exception sources vector number normal mode advanced mode priority res pin watchdog timer reset 0 h'0000 to h'0001 h'000000 to h'000003 high ? reserved for system use 1 to 6 h'0002 to h'000d h'000004 to h'00001b external interrupt pin nmi 7 h'000e to h'000f h'00001c to h'00001f cpu trap instruction #0 8 h'0010 to h'0011 h'000020 to h'000023 trap instruction #1 9 h'0012 to h'0013 h'000024 to h'000027 trap instruction #2 10 h'0014 to h'0015 h'000028 to h'00002b trap instruction #3 11 h'0016 to h'0017 h'00002c to h'00002f address break break conditions satisfied 12 h'0018 to h'0019 h'000030 to h'000033 cpu direct transition by executing the sleep instruction 13 h'001a to h'001b h'000034 to h'000037 external interrupt pin irq0 low-voltage detection interrupt 14 h'001c to h'001d h'000038 to h'00003b irq1 15 h'001e to h'001f h'00003c to h'00003f irq2 16 h'0020 to h'0021 h'000040 to h'000043 irq3 17 h'0022 to h'0023 h'000044 to h'000047 wkp 18 h'0024 to h'0025 h'000048 to h'00004b rtc overflow 19 h'0026 to h'0027 h'00004c to h'0004f low
section 3 exception handling rev. 3.00 sep. 10, 2007 page 47 of 528 rej09b0216-0300 relative module exception sources vector number normal mode advanced mode priority ? reserved for system use 20 h'0028 to h'0029 h'000050 to h'000057 high timer v timer v compare match a timer v compare match b timer v overflow 22 h'002c to h'002d h'000058 to h'00005b sci3 sci3 receive data full sci3 transmit data empty sci3 transmit end sci3 receive error 23 h'002e to h'002f h'00005c to h'00005f iic2 transmit data empty transmit end receive data full arbitration lost/overrun error nack detection stop conditions detected 24 h'0030 to h'0031 h'000060 to h'000063 a/d converter a/d conversion end 25 h'0032 to h'0033 h'000064 to h'000067 timer z compare match/input capture a0 to d0 timer z overflow 26 h'0034 to h'0035 h'000068 to h'00006b compare match/input capture a1 to d1 timer z overflow timer z underflow 27 h'0036 to h'0037 h'00006c to h'00006f ? reserved for system use 28 h'0038 to h'0039 h'000070 to h'000073 timer b1 timer b1 overflow 29 h'003a to h'003b h'000074 to h'000077 ? reserved for system use 30, 31 h'003c to h'003f h'000078 to h'00007f sci3_2 receive data full transmit data empty transmit end receive error 32 h'0040 to h'0041 h'000080 to h'000083 ? reserved for system use 33 h'0042 to h'0043 h'000084 to h'000087 clock source switching clock source switching (from external clock to on-chip oscillator) 34 h'0044 to h'0045 h'000088 to h'00008b low note: * a low-voltage detection interrupt is enabled only in the product with an on-chip power- on reset and low-voltage detection circuit.
section 3 exception handling rev. 3.00 sep. 10, 2007 page 48 of 528 rej09b0216-0300 3.2 register descriptions interrupts are controlled by the following registers. ? interrupt edge select register 1 (iegr1) ? interrupt edge select register 2 (iegr2) ? interrupt enable register 1 (ienr1) ? interrupt enable register 2 (ienr2) ? interrupt flag register 1 (irr1) ? interrupt flag register 2 (irr2) ? wakeup interrupt flag register (iwpr) 3.2.1 interrupt edge select register 1 (iegr1) iegr1 selects the direction of an edge that generates interrupt requests of pins nmi and irq3 to irq0 . bit bit name initial value r/w description 7 nmieg 0 r/w nmi edge select 0: falling edge of nmi pin input is detected 1: rising edge of nmi pin input is detected 6 to 4 ? all 1 ? reserved these bits are always read as 1. 3 ieg3 0 r/w irq3 edge select 0: falling edge of irq3 pin input is detected 1: rising edge of irq3 pin input is detected 2 ieg2 0 r/w irq2 edge select 0: falling edge of irq2 pin input is detected 1: rising edge of irq2 pin input is detected 1 ieg1 0 r/w irq1 edge select 0: falling edge of irq1 pin input is detected 1: rising edge of irq1 pin input is detected 0 ieg0 0 r/w irq0 edge select 0: falling edge of irq0 pin input is detected 1: rising edge of irq0 pin input is detected
section 3 exception handling rev. 3.00 sep. 10, 2007 page 49 of 528 rej09b0216-0300 3.2.2 interrupt edge select register 2 (iegr2) iegr2 selects the direction of an edge that generates interrupt requests of the pins adtrg and wkp5 to wkp0 . bit bit name initial value r/w description 7, 6 ? all 1 ? reserved these bits are always read as 1. 5 wpeg5 0 r/w wkp5 edge select 0: falling edge of wkp5 ( adtrg ) pin input is detected 1: rising edge of wkp5 ( adtrg ) pin input is detected 4 wpeg4 0 r/w wkp4 edge select 0: falling edge of wkp4 pin input is detected 1: rising edge of wkp4 pin input is detected 3 wpeg3 0 r/w wkp3 edge select 0: falling edge of wkp3 pin input is detected 1: rising edge of wkp3 pin input is detected 2 wpeg2 0 r/w wkp2 edge select 0: falling edge of wkp2 pin input is detected 1: rising edge of wkp2 pin input is detected 1 wpeg1 0 r/w wkp1edge select 0: falling edge of wkp1 pin input is detected 1: rising edge of wkp1 pin input is detected 0 wpeg0 0 r/w wkp0 edge select 0: falling edge of wkp0 pin input is detected 1: rising edge of wkp0 pin input is detected
section 3 exception handling rev. 3.00 sep. 10, 2007 page 50 of 528 rej09b0216-0300 3.2.3 interrupt enable register 1 (ienr1) ienr1 enables direct transition interrupts, rt c interrupts, and external pin interrupts. bit bit name initial value r/w description 7 iendt 0 r/w direct transfer interrupt enable when this bit is set to 1, direct transition interrupt requests are enabled. 6 ienta 0 r/w rtc interrupt enable when this bit is set to 1, rtc interrupt requests are enabled. 5 ienwp 0 r/w wakeup interrupt enable this bit is an enable bit, which is common to the pins wkp5 to wkp0 . when the bit is set to 1, interrupt requests are enabled. 4 ? 1 ? reserved this bit is always read as 1. 3 ien3 0 r/w irq3 interrupt enable when this bit is set to 1, interrupt requests of the irq3 pin are enabled. 2 ien2 0 r/w irq2 interrupt enable when this bit is set to 1, interrupt requests of the irq2 pin are enabled. 1 ien1 0 r/w irq1 interrupt enable when this bit is set to 1, interrupt requests of the irq1 pin are enabled. 0 ien0 0 r/w irq0 interrupt enable when this bit is set to 1, interrupt requests of the irq0 pin are enabled. when disabling interrupts by clearing bits in an interrupt enable register, or when clearing bits in an interrupt flag register, always do so while interrupts are masked (i = 1). if the above clear operations are performed while i = 0, and as a resu lt a conflict arises betw een the clear instruction and an interrupt request, exception handling for the interrupt will be executed after the clear instruction has been executed.
section 3 exception handling rev. 3.00 sep. 10, 2007 page 51 of 528 rej09b0216-0300 3.2.4 interrupt enable register 2 (ienr2) ienr2 enables, timer b1 overflow interrupts. bit bit name initial value r/w description 7, 6 ? all 0 ? reserved these bits are always read as 0. 5 ientb1 0 r/w timer b1 interrupt enable when this bit is set to 1, timer b1 overflow interrupt requests are enabled. 4 to 0 ? all 1 ? reserved these bits are always read as 1. when disabling interrupts by clearing bits in an interrupt enable register, or when clearing bits in an interrupt flag register, always do so while interrupts are masked (i = 1). if the above clear operations are performed while i = 0, and as a resu lt a conflict arises betw een the clear instruction and an interrupt request, exception handling for the interrupt will be executed after the clear instruction has been executed. 3.2.5 interrupt flag register 1 (irr1) irr1 is a status flag register for direct transition interrupts, rtc interrupts, and irq3 to irq0 interrupt requests. bit bit name initial value r/w description 7 irrdt 0 r/w direct transfer interrupt request flag [setting condition] when a direct transfer is made by executing a sleep instruction while dton in syscr2 is set to 1. [clearing condition] when irrdt is cleared by writing 0
section 3 exception handling rev. 3.00 sep. 10, 2007 page 52 of 528 rej09b0216-0300 bit bit name initial value r/w description 6 irrta 0 r/w rtc interrupt request flag [setting condition] when the rtc counter value overflows [clearing condition] when irrta is cleared by writing 0 5, 4 ? all 1 ? reserved these bits are always read as 1. 3 irri3 0 r/w irq3 interrupt request flag [setting condition] when irq3 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when irri3 is cleared by writing 0 2 irri2 0 r/w irq2 interrupt request flag [setting condition] when irq2 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when irri2 is cleared by writing 0 1 irri1 0 r/w irq1 interrupt request flag [setting condition] when irq1 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when irri1 is cleared by writing 0 0 irrl0 0 r/w irq0 interrupt request flag [setting condition] when irq0 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when irri0 is cleared by writing 0
section 3 exception handling rev. 3.00 sep. 10, 2007 page 53 of 528 rej09b0216-0300 3.2.6 interrupt flag register 2 (irr2) irr2 is a status flag register for timer b1 overflow interrupts. bit bit name initial value r/w description 7, 6 ? all 0 ? reserved these bits are always read as 0. 5 irrtb1 0 r/w timer b1 interrupt request flag [setting condition] when the timer b1 counter value overflows [clearing condition] when irrtb1 is cleared by writing 0 4 to 0 ? all 1 ? reserved these bits are always read as 1. 3.2.7 wakeup interrupt flag register (iwpr) iwpr is a status flag register for wkp5 to wkp0 interrupt requests. bit bit name initial value r/w description 7, 6 ? all 1 ? reserved these bits are always read as 1. 5 iwpf5 0 r/w wkp5 interrupt request flag [setting condition] when wkp5 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when iwpf5 is cleared by writing 0. 4 iwpf4 0 r/w wkp4 interrupt request flag [setting condition] when wkp4 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when iwpf4 is cleared by writing 0.
section 3 exception handling rev. 3.00 sep. 10, 2007 page 54 of 528 rej09b0216-0300 bit bit name initial value r/w description 3 iwpf3 0 r/w wkp3 interrupt request flag [setting condition] when wkp3 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when iwpf3 is cleared by writing 0. 2 iwpf2 0 r/w wkp2 interrupt request flag [setting condition] when wkp2 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when iwpf2 is cleared by writing 0. 1 iwpf1 0 r/w wkp1 interrupt request flag [setting condition] when wkp1 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when iwpf1 is cleared by writing 0. 0 iwpf0 0 r/w wkp0 interrupt request flag [setting condition] when wkp0 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when iwpf0 is cleared by writing 0.
section 3 exception handling rev. 3.00 sep. 10, 2007 page 55 of 528 rej09b0216-0300 3.3 reset exception handling when the res pin goes low, all processing halts and this lsi enters the reset. the internal state of the cpu and the registers of the on-chip peripheral modules are initialized by the reset. to ensure that this lsi is reset at power-up, hold the res pin low until the clock pulse generator output stabilizes. to reset the chip during operation, hold the res pin low for at least 10 system clock cycles. when the res pin goes high after being held low for the necessary time, this lsi starts reset exception handling. the reset exception handling sequence is shown in figure 3.1. however, for the reset exception handling sequence of the product with on-chip power-on reset circuit, refer to section 19, band-gap circuit, power-on reset, and low-voltage detection circuits. the reset exception handling sequence is as follows: 1. set the i bit in the condition code register (ccr) to 1. 2. the cpu generates a reset exception handling vector address, the data in that address is sent to the program counter (pc) as the start address, and program execution starts from that address. the reset exception handling vector address is h'0000 to h'0001 for normal mode operation and h'000000 to h'000003 in advanced mode operation.
section 3 exception handling rev. 3.00 sep. 10, 2007 page 56 of 528 rej09b0216-0300 3.4 interrupt exception handling 3.4.1 external interrupts as the external interrupts, there are nmi, irq3 to irq0, and wkp5 to wkp0 interrupts. (1) nmi interrupt nmi interrupt is requested by input signal edge to pin nmi . this interrupt is detected by either rising edge sensing or falling edge sensing, depending on the setting of bit nmieg in iegr1. nmi is the highest-priority interrupt, and can always be accepted wit hout depending on the i bit value in ccr. (2) irq3 to irq0 interrupts irq3 to irq0 interrupts are requested by input signals to pins irq3 to irq0 . these four interrupts are given different vector addresses, and are detected individually by either rising edge sensing or falling edge sensing, depending on the settings of bits ieg3 to ieg0 in iegr1. when pins irq3 to irq0 are designated for interrupt input in pmr1 and the designated signal edge is input, the corresponding bit in irr1 is set to 1, requesting the cpu of an interrupt. these interrupts can be masked by setting bits ien3 to ien0 in ienr1. (3) wkp5 to wkp0 interrupts wkp5 to wkp0 interrupts are requested by input signals to pins wkp 5 to wkp 0. these six interrupts have the same vector addresses, and are detected individually by either rising edge sensing or falling edge sensing, depending on the settings of bits wpeg5 to wpeg0 in iegr2. when pins wkp5 to wkp0 are designated for interrupt input in pmr5 and the designated signal edge is input, the corresponding bit in iwpr is set to 1, requesting the cpu of an interrupt. these interrupts can be masked by setting bit ienwp in ienr1.
section 3 exception handling rev. 3.00 sep. 10, 2007 page 57 of 528 rej09b0216-0300 res internal address bus internal read signal internal write signal internal data bus (16 bits) (1) reset exception handling vector address (h'0000) (2) program start address (3) initial program instruction (2) (1) (3) (2) reset cleared reset cleared vector fetch initial program instruction prefetch internal processing res internal address bus normal mode operation advanced mode operation internal read signal internal write signal internal data bus (16 bits) (1), (3) reset exception handling vector address ((1) = h'000000 (3) = h'000002) (2), (4) start address (contents of reset exception handling vector address) (5) start address (6) initial program instruction (2) (4) (6) (1) (3) (5) vector fetch initial program instruction prefetch internal processing figure 3.1 reset sequence
section 3 exception handling rev. 3.00 sep. 10, 2007 page 58 of 528 rej09b0216-0300 3.4.2 internal interrupts each on-chip peripheral module has a flag to show th e interrupt request status and the enable bit to enable or disable the interrupt. for rtc interrupt requests and direct transfer interrupt requests generated by execution of a sleep instruction, th is function is included in irr1, irr2, ienr1, and ienr2. when an on-chip peripheral module requests an interrupt, the corresponding interrupt request status flag is set to 1, requesting the cpu of an interrupt. these interrupts can be masked by writing 0 to clear the corresponding enable bit. 3.4.3 interrupt handling sequence interrupts are controlled by an interrupt controller. interrupt operation is described as follows. 1. if an interrupt occurs while the nmi or interrupt enable bit is set to 1, an interrupt request signal is sent to the interrupt controller. 2. when multiple interrupt requests are generated, the interrupt controller requests to the cpu for the interrupt handling with the highest priority at that time according to table 3.1. other interrupt requests are held pending. 3. the cpu accepts the nmi and address break w ithout depending on the i bit value. other interrupt requests are accepted, if the i bit is cleared to 0 in ccr; if the i bit is set to 1, the interrupt request is held pending. 4. if the cpu accepts the interrup t after processing of the curren t instruction is completed, interrupt exception handling will begin. first, both pc and ccr are pushed onto the stack. the state of the stack at this time is shown in figure 3.2. the pc value pushed onto the stack is the address of the first instruction to be executed upon return from interrupt handling. 5. then, the i bit of ccr is set to 1, masking further interrupts excluding the nmi and address break. upon return from interrupt handling, the values of i bit and other bits in ccr will be restored and returned to the values prior to the start of interrupt exception handling. 6. next, the cpu generates the vector addr ess corresponding to the accepted interrupt, and transfers the address to pc as a start address of the interrupt handling-routine. then a program starts executing from the address indicated in pc. figure 3.3 shows a typical interrupt sequence where the program area is in the on-chip rom and the stack area is in the on-chip ram.
section 3 exception handling rev. 3.00 sep. 10, 2007 page 59 of 528 rej09b0216-0300 stack area sp - 4 sp - 3 sp - 2 sp - 1 sp (r7) sp (r7) sp + 1 sp + 2 sp + 3 sp + 4 ccr ccr * pch pcl prior to start of interrupt exception handling after completion of interrupt exception handling even address [legend] normal mode operation pce: pch: pcl: ccr: sp: bits 23 to 16 of program counter (pc) bits 15 to 8 of program counter (pc) bits 7 to 0 of program counter (pc) condition code register stack pointer notes: 1. pc shows the address of the first instruction to be executed upon return from the interrupt handling routine. 2. register contents must always be saved and restored in word units, starting from an even-numbered address. * ignored when returning from the interrupt handling routine. pc and ccr saved to stack stack area sp - 4 sp - 3 sp - 2 sp - 1 sp (r7) sp (r7) sp + 1 sp + 2 sp + 3 sp + 4 ccr pce pch pcl prior to start of interrupt exception handling after completion of interrupt exception handling even address pc and ccr saved to stack advanced mode operation figure 3.2 stack status after exception handling
section 3 exception handling rev. 3.00 sep. 10, 2007 page 60 of 528 rej09b0216-0300 3.4.4 interrupt response time table 3.2 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handling-routine is executed. table 3.2 interrupt wait states item states total waiting time for completion of executing instruction * 1 1 to 23 15 to 37 saving of pc and ccr to stack 4 (17 to 39) * 2 vector fetch 2 (4) * 2 instruction fetch 4 internal processing 4 notes: 1. not including eepmov instruction. 2. the value in parentheses is the number of states in advance mode.
section 3 exception handling rev. 3.00 sep. 10, 2007 page 61 of 528 rej09b0216-0300 interrupt request signal normal mode operation advanced mode operation internal address bus internal read signal internal write signal internal data bus (16 bits) interrupt level decision and wait for end of instruction prefetch instruction of interrupt handling routine interrupt is accepted instruction prefetch stack access vector fetch internal processing internal processing (1) (2) (4) (1) (7) (9) (10) (3) (5) (6) (8) (9) (1) instruction prefetch address (instruction is not executed. address is saved as pc contents, becoming return address.) (2), (4) instruction code (instruction is not executed.) (3) instruction prefetch address (instruction is not executed.) (5) sp - 2 (6) sp - 4 (7) ccr (8) vector address (9) start address of interrupt handling routine (contents of vector) (10) first instruction of interrupt handling routine. (14) (12) (6) (4) high level (2) (1) (5) (7) (9) (11) (13) prefetch instruction of interrupt handling routine internal processing vector fetch stack access instruction prefetch internal processing interrupt level decision and wait for end of instruction interrupt is accepted interrupt request signal internal address bus internal read signal internal write signal internal data bus (3) (1) instruction prefetch address (instruction is not executed. address is saved as pc contents, becoming return address.) (2), (4) instruction code (instruction is not executed.) (3) instruction prefetch address (instruction is not executed.) (5) sp - 2 (7) sp - 4 (6), (8) saved pc and ccr (9), (11) vector address (10), (12) start address of interrupt handling routine (contents of vector) (13) start address of interrupt handling routine ((13), (10), (12)) (14) first instruction of interrupt handling routine. (8) (10) figure 3.3 interrupt sequence
section 3 exception handling rev. 3.00 sep. 10, 2007 page 62 of 528 rej09b0216-0300 3.5 usage notes 3.5.1 interrupts after reset if an interrupt is accepted after a reset and before the stack pointer (sp) is initialized, the pc and ccr will not be saved correctly, leading to a program crash. to prevent this, all interrupt requests, including nmi, are disabled immedi ately after a reset. since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: mov.w #xx: 16, sp). 3.5.2 notes on stack area use when word data is accessed, the l east significant bit of the address is regarded as 0. access to the stack always takes place in word size, so the st ack pointer (sp: r7) shoul d never indicate an odd address. use push rn (mov.w rn, @?sp) or pop rn (mov.w @sp+, rn) to save or restore register values. 3.5.3 notes on rewriting port mode registers when a port mode register is rewritten to switch the functions of external interrupt pins, irq3 to irq0 , and wkp5 to wkp0 , the interrupt request flag may be set to 1. when switching a pin function, mask the interrupt before setting the bit in the port mode register. after accessing the port mode register, execute at l east one instruction (e.g., nop), then clear the interrupt request flag from 1 to 0. figure 3.4 shows a port mode register setting and interrupt request flag clearing procedure. ccr i bit 1 set port mode register bit execute nop instruction interrupts masked. (another possibility is to disable the relevant interrupt in interrupt enable register 1.) after setting the port mode register bit, first execute at least one instruction (e.g., nop), then clear the interrupt request flag to 0. interrupt mask cleared clear interrupt request flag to 0 ccr i bit 0 figure 3.4 port mode register setting a nd interrupt request flag clearing procedure
section 4 address break abk0001a_000020020200 rev. 3.00 sep. 10, 2007 page 63 of 528 rej09b0216-0300 section 4 address break the address break simplifies on-board program de bugging. it requests an address break interrupt when the set break condition is satisfied. the interr upt request is not affected by the i bit of ccr. break conditions that can be set include inst ruction execution at a specific address and a combination of access and data at a specific a ddress. with the address break function, the execution start point of a program containing a b ug is detected and execution is branched to the correcting program. figure 4.1 shows a block diagram of the address break. barh barl bdrh bdrl abrkcr abrksr internal address bus comparator interrupt generation control circuit internal data bus comparator interrupt [legend] bare * , barh, barl: break address registers bdrh, bdrl: break data registers abrkcr: address break control register abrksr: address break status register bare * note: * only provided for microcontrollers that support advanced mode. figure 4.1 block diagram of address break
section 4 address break rev. 3.00 sep. 10, 2007 page 64 of 528 rej09b0216-0300 4.1 register descriptions address break has the following registers. ? address break control register (abrkcr) ? address break status register (abrksr) ? break address register (barh, barl) ? break data register (bdrh, bdrl) 4.1.1 address break cont rol register (abrkcr) abrkcr sets address break conditions. bit bit name initial value r/w description 7 rtinte 1 r/w rte interrupt enable when this bit is 0, the interrupt immediately after executing rte is masked and then one instruction must be executed. when this bit is 1, the interrupt is not masked. 6 5 csel1 csel0 0 0 r/w r/w condition select 1 and 0 these bits set address break conditions. 00: instruction execution cycle 01: cpu data read cycle 10: cpu data write cycle 11: cpu data read/write cycle
section 4 address break rev. 3.00 sep. 10, 2007 page 65 of 528 rej09b0216-0300 bit bit name initial value r/w description 4 3 2 acmp2 acmp1 acmp0 0 0 0 r/w r/w r/w address compare condition select 2 to 0 these bits set the comparison condition between the address set in bar and the internal address bus. normal mode 000: compares 16-bit addresses 001: compares the higher-order 12 bits of the addresses 010: compares the higher-order 8 bits of the addresses 011: compares the higher-order 4 bits of the addresses 1xx: reserved (setting prohibited) advanced mode 000: compares 24-bit addresses 001: compares the higher-order 20 bits of the addresses 010: compares the higher-order 16 bits of the addresses 011: compares the higher-order 12 bits of the addresses 1xx: reserved (setting prohibited) 1 0 dcmp1 dcmp0 0 0 r/w r/w data compare condition select 1 and 0 these bits set the comparison condition between the data set in bdr and the internal data bus. 00: no data comparison 01: compares lower 8-bit data between bdrl and data bus 10: compares upper 8-bit data between bdrh and data bus 11: compares 16-bit data between bdr and data bus [legend] x: don't care.
section 4 address break rev. 3.00 sep. 10, 2007 page 66 of 528 rej09b0216-0300 when an address break is set in the data read cycle or data write cycle, the data bus used will depend on the combination of the byte/word acce ss and address. table 4.1 shows the access and data bus used. when an i/o register space with an 8-bit data bus width is accessed in word size, a byte access is generated twice. for details on data widths of each register, see section 21.1, register addresses (address order). table 4.1 access and data bus used word access byte access even address odd address even address odd address rom space upper 8 bits lower 8 bits upper 8 bits upper 8 bits ram space upper 8 bits lower 8 bits upper 8 bits upper 8 bits i/o register with 8-bit data bus width upper 8 bits upper 8 bits upper 8 bits upper 8 bits i/o register with 16-bit data bus width upper 8 bits lower 8 bits ? ?
section 4 address break rev. 3.00 sep. 10, 2007 page 67 of 528 rej09b0216-0300 4.1.2 address break status register (abrksr) abrksr consists of the address break interrupt fl ag and the address break interrupt enable bit. bit bit name initial value r/w description 7 abif 0 r/w address break interrupt flag [setting condition] when the condition set in abrkcr is satisfied [clearing condition] when 0 is written after abif=1 is read 6 abie 0 r/w address break interrupt enable when this bit is 1, an address break interrupt request is enabled. 5 to 0 ? all 1 ? reserved these bits are always read as 1. 4.1.3 break address registers (bare, barh, barl) settings of the address where an address-break interrupt is to be generated are made in the break address registers (bar: bare*, barh and barl). for microcontrollers that support normal- mode operation, bar is a 16-bit readable/writable register with initial value h'ffff. for microcontrollers that support advanced-mode operation, bar is a 24-bit readable/writable register with the initial value h'ffffff. when setting an instruction execution cycle as the address break condition, set bar to the address of the first byte of the instruction. note: * bare is only provided for microcontrollers that support advanced-mode operation. 4.1.4 break data registers (bdrh, bdrl) bdrh and bdrl are 16-bit read/write registers that set the data for generating an address break interrupt. bdrh is compared with the upper 8-bit data bus. bdrl is compared with the lower 8- bit data bus. when memory or registers are accesse d by byte, the upper 8-bit data bus is used for even and odd addresses in the data transmission. therefore, comparison data must be set in bdrh for byte access. for word access, the data bus us ed depends on the address. see section 4.1.1, address break control register (abrkcr), for details. the initial value of this register is undefined.
section 4 address break rev. 3.00 sep. 10, 2007 page 68 of 528 rej09b0216-0300 4.2 operation when the abif and abie bits in abrksr are set to 1, the address break function generates an interrupt request to the cpu. the abif bit in abrksr is set to 1 by the combination of the address set in bar, the data set in bdr, and the conditions set in abrkcr. when the interrupt request is accepted, interrupt exception handling star ts after the instruction being executed ends. the address break interrupt is not masked by the i bit in ccr of the cpu. figures 4.2 show the operation examples of the address break interrupt setting. nop instruc- tion prefetch register setting abrkcr = h'80 bar = h'025a program 0258 025a 025c 0260 0262 : * nop nop mov.w @h'025a,r0 nop nop : 0258 address bus interrupt request 025a 025c 025e sp-2 sp-4 nop instruc- tion prefetch mov instruc- tion 1 prefetch mov instruc- tion 2 prefetch internal processing stack save interrupt acceptance underline indicates the address to be stacked. when the address break is specified in instruction execution cycle figure 4.2 address break in terrupt operation example (1)
section 4 address break rev. 3.00 sep. 10, 2007 page 69 of 528 rej09b0216-0300 mov instruc- tion 1 prefetch register setting abrkcr = h'a0 bar = h'025a program 0258 025a 025c 0260 0262 : * nop nop mov.w @h'025a,r0 nop nop : 025c address bus interrupt request 025e 0260 025a 0262 0264 sp-2 mov instruc- tion 2 prefetch nop instruc- tion prefetch mov instruc- tion execution next instru- ction prefetch internal processing stack save nop instruc- tion prefetch interrupt acceptance underline indicates the address to be stacked. when the address break is specified in the data read cycle figure 4.2 address break in terrupt operation example (2)
section 4 address break rev. 3.00 sep. 10, 2007 page 70 of 528 rej09b0216-0300
section 5 clock pulse generator cpg0200a_000020020200 rev. 3.00 sep. 10, 2007 page 71 of 528 rej09b0216-0300 section 5 clock pulse generator the clock pulse generator (cpg) consists of a system clock generating circuitry, a subclock generating circuitry, and two prescalers. the system clock generating circuitry includes an external clock oscillator, a duty correction circuit, an on-chip oscillator, an rc clock divider, a clock select circuit, and a system clock divide r. the subclock generating circuitry includes a subclock oscillator, and a subclock divider. the cpg can function as a clock generating circuitry itself or in combination with an external oscillator. figure 5.1 shows a block diagram of the clock pulse generator. external clock oscillator duty correction circuit system clock divider prescaler s (13 bits) osc1 osc2 osc osc /2 to /8192 /8 /16 /32 /64 on-chip oscillator clock select circuit rc clock divider r osc r osc rc r osc /2 r osc /4 subclock oscillator subclock divider prescaler w (5 bits) x 1 x 2 system clock generating circuitry w (f w ) w /2 w /4 sub w /8 w /8 to w /128 subclock generating circuitry figure 5.1 block diagram of clock pulse generator the system clock ( ) and subclock ( sub ) are basic clocks on which the cpu and on-chip peripheral modules operate. the system clock is divided into from /2 to /8192 by prescaler s. the subclock is divided into from w /8 to w /128 by prescaler w. these divided clocks are supplied to respective peripheral modules.
section 5 clock pulse generator rev. 3.00 sep. 10, 2007 page 72 of 528 rej09b0216-0300 5.1 features ? choice of two clock sources on-chip oscillator clock clock by an external oscillator output ? choice of two types of rc oscillation frequency by the user software 16 mhz 20 mhz ? frequency trimming since the initial frequency of the on-chip oscillator in the flash memory version is within the range of two frequencies shown above, it is normally unnecessary to trim the frequency. it is, however, still possible to adjust it by rewriting the trimming registers. ? backup of the external oscillation halt this system detects the external oscillator halt. if detected, the system clock source is automatically switched to the on-chip oscillator clock. ? interrupt can be requested to the cpu when the system clock is switched from the external clock to the on-chip oscillator clock. 5.2 register descriptions the cpg has the following registers. ? rc control register (rccr) ? rc trimming data protect register (rctrmdpr) ? rc trimming data register (rctrmdr) ? clock control/status register (ckcsr)
section 5 clock pulse generator rev. 3.00 sep. 10, 2007 page 73 of 528 rej09b0216-0300 5.2.1 rc control register (rccr) rccr controls the on-chip oscillator. bit bit name initial value r/w description 7 rcstp 0 r/w on-chip oscillator standby the on-chip oscillator standby state is entered by setting this bit to 1. 6 fsel 1 r/w frequency select for on-chip oscillator 0: 16 mhz 1: 20 mhz 5 vclsel 0 r/w power supply select for on-chip oscillator 0: selects vbgr 1: selects vcl when the vcl power is selected, the accuracy of the on- chip oscillator frequency cannot be guaranteed. 4 to 2 ? all 0 ? reserved these bits are always read as 0. 1 0 rcpsc1 rcpsc0 1 0 r/w r/w division ratio select for on-chip oscillator the division ratio of r osc changes right after rewriting this bit. these bits can be written to only when the cksta bit in ckcsr is 0. 0x: r osc (not divided) 10: r osc /2 11: r osc /4
section 5 clock pulse generator rev. 3.00 sep. 10, 2007 page 74 of 528 rej09b0216-0300 5.2.2 rc trimming data protect register (rctrmdpr) rctrmdpr controls rctrmdpr itself and writi ng to rctrmdr. use the mov instruction to rewrite this register. bit manipulation instruction cannot change the settings. bit bit name initial value r/w description 7 wri 1 w write inhibit only when writing 0 to this bit, this register can be written to. this bit is always read as 1. 6 prwe 0 r/w protect information write enable bits 5 and 4 can be written to when this bit is set to 1. [setting condition] ? when writing 0 to the wri bit and writing 1 to the prwe bit [clearing conditions] ? reset ? when writing 0 to the wri bit and writing 0 to the prwe bit 5 lockdw 0 r/w trimming data register lock down the rc trimming data register (rctrmdr) cannot be written to when this bit is set to 1. once this bit is set to 1, this register cannot be written to until a reset is input even if 0 is written to this bit. [setting condition] ? when writing 0 to the wri bit and writing 1 to the lockdw bit while the prwe bit is 1 [clearing condition] ? reset
section 5 clock pulse generator rev. 3.00 sep. 10, 2007 page 75 of 528 rej09b0216-0300 bit bit name initial value r/w description 4 trmdrwe 0 r/w trimming data register write enable this register can be written to when the lockdw bit is 0 and this bit is 1. [setting condition] ? when writing 0 to the wri bit while writing 1 to the trmdrwe bit while the prwe bit is 1 [clearing conditions] ? reset ? when writing 0 to the wri bit and writing 0 to the trmdrwe bit while the prwe bit is 1 3 to 0 ? all 1 ? reserved these bits are always read as 1. 5.2.3 rc trimming data register (rctrmdr) rctrmdr stores the trimming data of the on-chip oscillator frequency (fsel = 1, 20 mhz). bit bit name initial value r/w description 7 trmd7 (0) * r/w 6 trmd6 (0) * r/w 5 trmd5 (0) * r/w 4 trmd4 (0) * r/w 3 trmd3 (0) * r/w 2 trmd2 (0) * r/w 1 trmd1 (0) * r/w 0 trmd0 (0) * r/w trimming data (fsel = 1, 20 mhz) the trimming data is loaded from the flash memory to this register right after a reset. the on-chip oscillator clock (fsel = 1, 20 mhz) can be trimmed by changing these bits. the frequency of the on-chip oscillator clock changes right after writing these bits. these bits are initialized to h'00. changes in frequency are shown below (bit trmd7 is a sign bit). (min.) h'80 h'ff h'00 h'01 h'7f (max.) note: * these values are initialized to the trimming data loaded from the flash memory.
section 5 clock pulse generator rev. 3.00 sep. 10, 2007 page 76 of 528 rej09b0216-0300 5.2.4 clock control/status register (ckcsr) ckcsr selects the port c function, controls switching the system clocks, and indicates the system clock state. bit bit name initial value r/w description port c function select 1 and 2 pmrc1 pmrc0 pc1 pc0 0 0 i/o i/o 1 0 clkout i/o 0 1 (open) osc1 (external clock input) 1 1 osc2 osc1 7 6 pmrc1 pmrc0 0 0 r/w r/w 5 oscbake 0 r/w external clock backup enable 0: external clock backup disabled 1: external clock backup enabled the external oscillation detecting circuit is enabled when this bit is 1. when the external oscillator halt is detected while this lsi operates on the external input signal, the system clock source is automatically switched to the on- chip oscillator regardless of the value of bit 4 in this register. note: the external oscillation detecting circuit operates on the on-chip oscillator clock. when this bit is set to 1, do not set the on-chip oscillator to the standby mode by the rcstp bit in rccr.
section 5 clock pulse generator rev. 3.00 sep. 10, 2007 page 77 of 528 rej09b0216-0300 bit bit name initial value r/w description 4 oscsel 0 r/w lsi operating clock select ? when oscbake = 0 this bit is used to forcibly select the system clock of this lsi. 0: the on-chip oscillator clock selected as the system clock source 1: the external input selected as the system clock source ? when oscbake = 1 this bit is used to switch the on-chip oscillator clock to the external clock. while this lsi is operating on the on-chip oscillator clock, setting this bit to 1 switches the system clocks to the external clock. [setting condition] ? when 1 is written to this bit while ckswif = 0 [clearing conditions] ? when 0 is written to this bit ? when the external oscillator halt is detected while oscbake = 1 3 ckswie 0 r/w clock switching interrupt enable setting this bit to 1 enables the clock switching interrupt request. 2 ckswif 0 r/w clock switching interrupt request flag [setting condition] ? when the external clock is switched to the on-chip oscillator clock as the system clock source [clearing condition] ? when writing 0 after reading as 1
section 5 clock pulse generator rev. 3.00 sep. 10, 2007 page 78 of 528 rej09b0216-0300 bit bit name initial value r/w description 1 oschlt 1 r external oscillator halt detecting flag ? when oscbake = 1 this bit indicates the checking result of the external oscillator state. 0: external oscillator is running 1: external oscillator is halted. ? when oscbake = 0 this bit is non-deterministic; always read as 1. 0 cksta 0 r lsi operating clock status 0: this lsi operates on the on-chip oscillator clock. 1: this lsi operates on the external clock.
section 5 clock pulse generator rev. 3.00 sep. 10, 2007 page 79 of 528 rej09b0216-0300 5.3 system clock select operation figure 5.2 shows the state transition of the system clock. reset state lsi operates on on-chip oscillator clock on-chip oscillator: operated external oscillator: halted switching to external clock on-chip oscillator: halted external oscillator: operated on-chip oscillator: operated external oscillator: operated oscillator halted oscillator operated lsi operates on external oscillator reset release note: * conditions for the state transition are as follows: ? when the external oscillator halt is detected while the backup function is enabled ? when the external clock is switched to the on-chip oscillator clock by user software while the backup function is disabled * figure 5.2 state transition of system clock 5.3.1 clock control operation the lsi system clock is generated by the on-chip oscillator clock after a reset. the system clock sources are switched from the on-chip oscillator to the external clock by the user software. figure 5.3 shows the flowchart to switch clocks with the external clock backup function enabled. figures 5.4 and 5.5 show the flowcharts to switch clocks with the external clock backup function disabled.
section 5 clock pulse generator rev. 3.00 sep. 10, 2007 page 80 of 528 rej09b0216-0300 external oscillation starts to be enabled when pins pc1 and pc0 are specified as external clock pins. write 0 to bit pmrc1 to input the external clock. the external oscillator halt detecting circuit is enabled when the external oscillation backup function is enabled. since this detecting circuit operates on the on-chip oscillator clock, do not set the on-chip oscillator to standby mode by using the rcstp bit in rccr. an interrupt to switch from the on-chip oscillator clock to the external oscillator is enabled. after writing 1 to the oscsel bit, this lsi waits until the oscillation of the external oscillator settles. the correspondence between nwait, which is the number of wait cycles for oscillation settling, and nstby, which is the number of wait cycles for oscillation settling when returning from standby mode, is as follows: nstby nwait 2 nstby nstby is set by bits sts[2:0] in syscr1. for details, see section 6.1.1, system control register 1 (syscr1). while waiting for external oscillation settling, this lsi is not halted but continues to operate on the on- chip oscillator clock. read the cksta bit in ckcsr to ensure whether or not clocks are switched. when the oscillation settles, this lsi switches the system clocks to the external clock. if the external oscillator is halted, then set the clock switching interrupt request flag. if this lsi detects the external oscillator halt, it switches the system clocks to the on-chip oscillator clock, and sets the clock switching interrupt request flag. [1] [2] [3] [4] [5] [6] yes no [1] [2] [3] exception handling for clock switching lsi operates on on-chip oscillator clock start (reset) write 1 to pmrc0 in ckcsr write 1 to pmrc1 in ckcsr write 1 to oscbake in ckcsr clear ckswif in ckcsr to 0 write 1 to ckswie in ckcsr write 1 to oscsel in ckcsr switched to external clock? (cksta in ckcsr is 1) lsi operates on external clock external oscillator halt is detected * [4] [5] [6] note: * to prevent the lsi from malfunctioning at the external oscillation halt, switching the clock source along with the watchdog timer is highly recommended. external oscillator halt is detected * lsi operates on on-chip oscillator clock figure 5.3 flowchart of clock switching with backup function enabled
section 5 clock pulse generator rev. 3.00 sep. 10, 2007 page 81 of 528 rej09b0216-0300 yes no [1] lsi operates on on-chip oscillator clock start (reset) write 1 to pmrc0 in ckcsr write 1 to pmrc1 in ckcsr write 0 to ckswif in ckcsr write 1 to oscsel in ckcsr switched to external clock? (cksta in ckcsr is 1) lsi operates on external oscillator [2] [3] external oscillation starts to be enabled when pins pc1 and pc0 are specified as external clock pins. write 0 to bit pmrc1 to input the external clock. after writing 1 to the oscsel bit, this lsi waits until the oscillation of the external oscillator settles. the correspondence between nwait, which is the number of wait cycles for oscillation settling, and nstby, which is the number of wait cycles for oscillation settling when returning from standby mode, is as follows: nstby nwait 2 nstby nstby is set by bits sts[2:0] in syscr1. for details, see section 6.1.1, system control register 1 (syscr1). while the system is waiting for the external oscillation settling, this lsi is not halted but continues to operate on the on-chip oscillator clock. read the value of the cksta bit in ckcsr to ensure that the system clocks are switched. [1] [2] [3] figure 5.4 flowchart of clock switching with backup function disabled (1) (from on-chip oscillator clock to external clock)
section 5 clock pulse generator rev. 3.00 sep. 10, 2007 page 82 of 528 rej09b0216-0300 [1] [2] exception handling for clock switching lsi operates on external clock start (lsi operates on external clock) write 0 to oscsel in ckcsr lsi operates on on-chip oscillator clock write 0 to oscbake in ckcsr write 1 to ckswie in ckcsr if necessary write 0 to pmrc0 in ckcsr if necessary lsi operates on on-chip oscillator clock when ckswie = 1 when 0 is written to the oscsel bit, this lsi switches from the external clock to the on-chip oscillator clock after a stop duration. the halt duration here is the duration while the rc clock rises seven times after the oscsel bit becomes 0. writing 0 to pmrc0 disables the external oscillation input. [1] [2] figure 5.5 flowchart of clock switching with backup function disabled (2) (from external clock to on-chip oscillator clock)
section 5 clock pulse generator rev. 3.00 sep. 10, 2007 page 83 of 528 rej09b0216-0300 5.3.2 clock switching timing the timing for switching clocks are shown in figures 5.6 to 5.8. [legend] osc: external clock rc: on-chip oscillator clock : system clock oscsel: bit 4 in ckcsr phistop: system clock stop control signal cksta: bit 0 in ckcsr wait for external oscillation settling halt * external clock operation note: * the halt duration is the duration from the timing when the clock stops to the first rising edge of the osc clock after seven clock cycles of the rc clock have elapsed. osc nwait rc phistop (internal signal) oscsel cksta on-chip oscillator clock operation figure 5.6 timing chart of switching from on-chip oscillator clock to external clock
section 5 clock pulse generator rev. 3.00 sep. 10, 2007 page 84 of 528 rej09b0216-0300 [legend] osc: external clock rc: on-chip oscillator clock : system clock oscsel: bit 4 in ckcsr phistop: system clock stop control signal cksta: bit 0 in ckcsr ckswif: bit 2 in ckcsr halt * on-chip oscillator clock operation note: * the halt duration is the duration from the timing when the clock stops to the seventh rising edge of the rc clock. osc rc phistop (internal signal) oscsel cksta external rc clock operation ckswif figure 5.7 timing chart to switch from external clock to on-chip oscillator clock
section 5 clock pulse generator rev. 3.00 sep. 10, 2007 page 85 of 528 rej09b0216-0300 t chk [legend] osc: external clock rc: on-chip oscillator clock : system clock oschlt: bit 1 in ckcsr phistop: system clock stop control signal cksta: bit 0 in ckcsr ckswif: bit 2 in ckcsr halt * 2 on-chip oscillator clock operation notes: 1. 44 rc t chk 48 rc 2. the halt duration is the duration from the timing when the clock stops to the seventh rising edge of the rc clock. osc rc phistop (internal signal) oschlt cksta external clock operation ckswif external clock halt osc halt detected * 1 figure 5.8 external oscillation backup timing
section 5 clock pulse generator rev. 3.00 sep. 10, 2007 page 86 of 528 rej09b0216-0300 5.4 trimming of on-chi p oscillator frequency users can trim the on-chip oscillator clock, suppl ying the external referen ce pulses with the input capture function in internal timer z. an example of trimming flow and a timing chart are shown in figures 5.9 and 5.10, respectively. because rctr mdr is initialized by a reset, when users have trimmed the frequencies, some operations after a reset are necessary, such as trimming it again or saving the trimming value in an external device for later reloading. yes no note: * comparing the difference between the measured frequency and the desired frequency, individual bits of rctrmdr are decided from the msb bit by bit. start setting timer z gra: input capture grc: buffer of gra set rctrmdr to h'00 input reference pulses to pin p60/ftioa0 capture 1 capture 2 frequency calculation within desired frequency range? end modify rctrmdr * figure 5.9 example of trimming flow for on-chip oscillator clock
section 5 clock pulse generator rev. 3.00 sep. 10, 2007 page 87 of 528 rej09b0216-0300 m nm n m m + 1 m + t a ( s) m ? 1 rc ftioa0 input capture input timer z tcnt gra_0 grc_0 capture 1 capture 2 m + figure 5.10 timing chart of trimming of on-chip oscillator frequency the on-chip oscillator frequency is gained by th e expression below. since the input-capture input is sampled by the rc clock, the calculated result may include a sampling error of 1 cycle of the rc clock. rc = (m + ) ? m (mhz) t a rc: frequency of on-chip oscillator (mhz) t a : period of reference clock ( s) m: timer z counter value
section 5 clock pulse generator rev. 3.00 sep. 10, 2007 page 88 of 528 rej09b0216-0300 5.5 external oscillators there are two methods to supply external clock pulses into this lsi: connecting a crystal or ceramic resonator, and an external clock. oscillation pins osc1 and osc2 are common with general ports pc0 and pc1, respectively. to set pins pc0 and pc1 as crystal resonator or external clock input ports, refer to section 5.2.4, clock control/status register (ckcsr). figure 5.11 shows a block diagram of an external clock oscillator. osc2 osc1 lpm * 1 600 k ? * 2 notes: 1. lpm: power-down mode (standby mode, subactive mode, or subsleep mode) 2. values here are reference values. figure 5.11 block diagram of external clock oscillator 5.5.1 connecting crystal resonator figure 5.12 shows an example of connecting a crystal resonator. an at-cut parallel-resonance crystal resonator should be used. figure 5.13 shows the equivalent circuit of a crystal resonator. a resonator having the characteristics given in table 5.1 should be used. c 1 c 2 pc0/osc1 pc1/osc2/clkout c = c = 10 to 22 pf 1 2 figure 5.12 example of connection to crystal resonator
section 5 clock pulse generator rev. 3.00 sep. 10, 2007 page 89 of 528 rej09b0216-0300 c s c o r s l s pc0/osc1 pc1/osc2/clkout figure 5.13 equivalent circuit of crystal resonator table 5.1 crystal resonator parameters frequency (mhz) 4 8 10 16 20 r s (max.) 120 ? 80 ? 60 ? 50 ? 40 ? c o (max.) 70 pf 5.5.2 connecting ceramic resonator figure 5.14 shows an example of connecting a ceramic resonator. c 1 c 2 pc0/osc1 pc1/osc2/clkout c = c = 5 to 30 pf 1 2 figure 5.14 example of conn ection to cera mic resonator 5.5.3 inputting external clock to use the external clock, input the external clock on pin osc1. figure 5.15 shows an example of connection. the duty cycle of the external clock signal must range from 45 to 55%. pc0/osc1 pc1/osc2/clkout external clock input open figure 5.15 example of external clock input
section 5 clock pulse generator rev. 3.00 sep. 10, 2007 page 90 of 528 rej09b0216-0300 5.6 subclock oscillator figure 5.16 shows a block diagram of the subclock oscillator. note : resistance here is a reference value. 2 1 x 8 m ? x figure 5.16 block diagram of subclock oscillator 5.6.1 connecting 32.768-khz crystal resonator clock pulses can be supplied to the subclock divider by connecting a 32.768-khz crystal resonator, as shown in figure 5.17. figure 5.18 shows the equivalent circuit of the 32.768-khz crystal resonator. x x c 1 c 2 1 2 c = c = 15 pf (typ.) 12 figure 5.17 typical connection to 32.768-khz crystal resonator x 1 x 2 l s c s c o c o = 1.5 pf (typ.) r s = 14 k ? (typ.) f w = 32.768 khz r s note: values here are reference values. figure 5.18 equivalent circuit of 32.768-khz crystal resonator
section 5 clock pulse generator rev. 3.00 sep. 10, 2007 page 91 of 528 rej09b0216-0300 5.6.2 pin connection when not using subclock when the subclock is not used, connect pin x1 to vcl or vss and leave pin x2 open, as shown in figure 5.19. x 1 v cl or v ss x 2 open figure 5.19 pin connection when not using subclock 5.7 prescaler 5.7.1 prescaler s prescaler s is a 13-bit counter using the system clock ( ) as its input clock. the outputs, which are divided clocks, are used as internal clocks by the on-chip peripheral modules. prescaler s is initialized to h'0000 by a reset, and starts counting on exit from the reset state. in standby mode and subsleep mode, the external clock oscillator st ops. prescaler s also stops and is initialized to h'0000. it cannot be read from or written to by the cpu. the outputs from prescaler s are shared by the on-chip peripheral modules. the division ratio can be set separately for each on-chip peripheral module. in active mode and sleep mode, the clock input to prescaler s is a system clock with the division ratio specified by bits ma2 to ma0 in syscr2. 5.7.2 prescaler w prescaler w is a 5-bit counter using a 32.768-khz signal divided by 4 as its input clock. the divided output is used for clock time base operation of the rtc. prescaler w is initialized to h'00 by a reset, and starts counting on exit from the reset state. even in standby mode, subactive mode, or subsleep mode, prescaler w continues functioning.
section 5 clock pulse generator rev. 3.00 sep. 10, 2007 page 92 of 528 rej09b0216-0300 5.8 usage notes 5.8.1 note on resonators resonator characteristics are closely related to board design and should be carefully evaluated by the user, referring to the examples shown in this section. resonator circuit parameters will differ depending on the resonator element, stray capacitance of the pcb, and other factors. suitable values should be determined in consultation with the resonator element manufacturer. design the circuit so that the resonator element never receives voltages exceeding its maximum rating. 5.8.2 notes on board design when using a crystal resonator (ceramic resonato r), place the resonator and its load capacitors as close as possible to pins osc1 and osc2. other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation (see figure 5.20). c 1 c 2 signal a signal b prohibited pc0/osc1 pc1/osc2/clkout figure 5.20 example of incorrect board design
section 6 power-down modes lpw3002a_000120030300 rev. 3.00 sep. 10, 2007 page 93 of 528 rej09b0216-0300 section 6 power-down modes this lsi has six modes of operation after a reset. these include a normal active mode and four power-down modes, in which power consumption is significantly reduced. module standby mode reduces power consumption by selectively halting on-chip module functions. ? active mode the cpu and all on-chip peripheral modules are operable on the system clock. the system clock frequency can be selected from osc, osc/8, osc/16, osc/32, and osc/64. ? subactive mode the cpu and all on-chip peripheral modules ar e operable on the subclock. the subclock frequency can be selected from w/2, w/4, and w/8. ? sleep mode the cpu halts. on-chip peripheral modu les are operable on the system clock. ? subsleep mode the cpu halts. on-chip peripheral modules are operable on the subclock. ? standby mode the cpu and all on-chip peripheral modules ha lt. when the clock time-base function is selected, the rtc is operable. ? module standby mode independent of the above modes, power c onsumption can be redu ced by halting on-chip peripheral modules that are not used in module units.
section 6 power-down modes rev. 3.00 sep. 10, 2007 page 94 of 528 rej09b0216-0300 6.1 register descriptions the registers related to power-down modes are listed below. ? system control register 1 (syscr1) ? system control register 2 (syscr2) ? module standby control register 1 (mstcr1) ? module standby control register 2 (mstcr2) 6.1.1 system control register 1 (syscr1) syscr1 controls the power-down modes, as well as syscr2. bit bit name initial value r/w description 7 ssby 0 r/w software standby this bit selects the mode to transit after the execution of the sleep instruction. 0: enters sleep mode or subsleep mode. 1: enters standby mode. for details, see table 6.2.
section 6 power-down modes rev. 3.00 sep. 10, 2007 page 95 of 528 rej09b0216-0300 bit bit name initial value r/w description 6 5 4 sts2 sts1 sts0 0 0 0 r/w r/w r/w standby timer select 2 to 0 these bits set the wait time from when the external clock oscillator starts functioning until the clock is supplied, in shifting from standby mode, subactive mode, or subsleep mode, to active mode or sleep mode. during the wait time, this lsi automatically selects the on-chip oscillator clock as its system clock and counts the number of wait states. select a wait time of 6.5 ms (oscillation stabilization time) or longer, depending on the operating frequency. table 6.1 shows the relationship between the sts2 to sts0 values and the wait time. when using an external clock, set the wait time to be 100 s or longer. these bits also set the wait states for external oscillation stabilization when system clock is switched from the on- chip oscillator clock to the external clock by user software. the relationship between nwait (number of wait states for oscillation stabilization) and nstby (number of wait states for recovering to the standby mode) is as follows. nstby nwait 2 nstby 3 nesel 0 r/w noise elimination sampling frequency select the subclock pulse generator generates the watch clock signal ( w ) and the external clock pulse generator generates the oscillator clock ( osc ). this bit selects the sampling frequency of the oscillator clock when the watch clock signal ( w ) is sampled. when osc = 4 to 20 mhz, clear nesel to 0. 0: sampling rate is osc /16 1: sampling rate is osc /4 2 to 0 ? all 0 ? reserved these bits are always read as 0.
section 6 power-down modes rev. 3.00 sep. 10, 2007 page 96 of 528 rej09b0216-0300 table 6.1 operating frequency and waiting time bit name operating frequency sts2 sts1 sts0 waiting time 20 mhz 16 mhz 10 mhz 8 mhz 5 mhz 4 mhz 0 0 0 8,192 states 0.4 0.5 0.8 1.0 1.6 2.0 1 16,384 states 0.8 1.0 1.6 2.0 3.3 4.1 1 0 32,768 states 1.6 2.0 3.3 4.1 6.6 8.2 1 65,536 states 3.3 4.1 6.6 8.2 13.1 16.4 1 0 0 131,072 states 6.6 8.2 13.1 16.4 26.2 32.8 1 1,024 states 0.05 0.06 0.10 0.13 0.20 0.26 1 0 128 states 0.00 0.00 0.01 0.02 0.03 0.03 1 16 states 0.00 0.00 0.00 0.00 0.00 0.00 note: time unit is ms.
section 6 power-down modes rev. 3.00 sep. 10, 2007 page 97 of 528 rej09b0216-0300 6.1.2 system control register 2 (syscr2) syscr2 controls the power-down modes, as well as syscr1. bit bit name initial value r/w description 7 6 5 smsel lson dton 0 0 0 r/w r/w r/w sleep mode selection low speed on flag direct transfer on flag these bits select the mode to enter after the execution of a sleep instruction, as well as bit ssby of syscr1. for details, see table 6.2. 4 3 2 ma2 ma1 ma0 0 0 0 r/w r/w r/w active mode clock select 2 to 0 these bits select the operating clock frequency in active and sleep modes. the operating clock frequency changes to the set frequency after the sleep instruction is executed. 0xx: osc 100: osc /8 101: osc /16 110: osc /32 111: osc /64 1 0 sa1 sa0 0 0 r/w r/w subactive mode clock select 1 and 0 these bits select the operating clock frequency in subactive and subsleep modes. the operating clock frequency changes to the set frequency after the sleep instruction is executed. 00: w /8 01: w /4 1x: w /2 [legend] x: don't care.
section 6 power-down modes rev. 3.00 sep. 10, 2007 page 98 of 528 rej09b0216-0300 6.1.3 module standby control register 1 (mstcr1) mstcr1 allows the on-chip peripheral modules to enter a standby state in module units. bit bit name initial value r/w description 7 ? 0 ? reserved this bit is always read as 0. 6 mstiic 0 r/w iic2 module standby iic2 enters standby mode when this bit is set to 1 5 msts3 0 r/w sci3 module standby sci3 enters standby mode when this bit is set to 1 4 mstad 0 r/w a/d converter module standby a/d converter enters standby mode when this bit is set to 1 3 mstwd 0 r/w watchdog timer module standby watchdog timer enters standby mode when this bit is set to 1.when the internal oscillator is selected for the watchdog timer clock, the watchdog timer operates regardless of the setting of this bit 2 ? 0 ? reserved this bit is always read as 0. 1 msttv 0 r/w timer v module standby timer v enters standby mode when this bit is set to 1 0 mstta 0 r/w rtc module standby rtc enters standby mode when this bit is set to 1
section 6 power-down modes rev. 3.00 sep. 10, 2007 page 99 of 528 rej09b0216-0300 6.1.4 module standby control register 2 (mstcr2) mstcr2 allows the on-chip peripheral modules to enter a standby state in module units. bit bit name initial value r/w description 7 msts3_2 0 r/w sci3_2 module standby sci3_2 enters standby mode when this bit is set to1 6, 5 ? all 0 ? reserved these bits are always read as 0. 4 msttb1 0 r/w timer b1 module standby timer b1 enters standby mode when this bit is set to1 3, 2 ? all 0 ? reserved these bits are always read as 0. 1 msttz 0 r/w timer z module standby timer z enters standby mode when this bit is set to1 0 mstpwm 0 r/w pwm module standby pwm enters standby mode when this bit is set to1
section 6 power-down modes rev. 3.00 sep. 10, 2007 page 100 of 528 rej09b0216-0300 6.2 mode transitions and states of lsi figure 6.1 shows the possible transitions among thes e operating modes. a transition is made from the program execution state to the program halt st ate by executing a sleep instruction. interrupts allow for returning from the program halt state to the program execution state. a direct transition between active mode and subactive mode, which are both program execution states, can be made without halting the program. the operating frequency can also be changed in the same modes by making a transition directly from active mode to active mode, and from subactive mode to subactive mode. res input enables transitions from a mode to the reset state. table 6.2 shows the transition conditions of each mode after the sleep instruction is executed and a mode to return by an interrupt. table 6.3 shows the inte rnal states of the lsi in each mode. reset state standby mode active mode sleep mode subsleep mode subactive mode program halt state program execution state program halt state sleep instruction sleep instruction interrupt direct transition interrupt direct transition interrupt notes: 1. to make a transition to another mode by an interrupt, make sure interrupt handling is after the interrupt is accepted. 2. details on the mode transition conditions are given in table 6.2. sleep instruction direct transition interrupt direct transition interrupt interrupt sleep instruction interrupt interrupt sleep instruction interrupt sleep instruction figure 6.1 mode transition diagram
section 6 power-down modes rev. 3.00 sep. 10, 2007 page 101 of 528 rej09b0216-0300 table 6.2 transition mode after sleep instruction execution and transition mode due to interrupt dton ssby smsel lson transition mode after sleep instruction execution transition mode due to interrupt 0 0 0 0 sleep mode active mode 1 subactive mode 1 0 subsleep mode active mode 1 subactive mode 1 x x standby mode active mode 1 x 0 * 0 active mode (direct transition) ? x x 1 subactive mode (direct transition) ? x: don?t care. note: * when a state transition is performed while smsel is 1, timer v, sci3, sci3_2 and the a/d converter are reset, and all registers are set to their initial values. to use these functions after entering active mode, reset the registers.
section 6 power-down modes rev. 3.00 sep. 10, 2007 page 102 of 528 rej09b0216-0300 table 6.3 internal state in each operating mode function active mode sleep mode subactive mode subsleep mode standby mode external clock oscillator functioning functioning halted halted halted subclock oscillator functioning function ing functioning functioning functioning instructions functioning halted functioning halted halted cpu operations registers functioning retained functioning retained retained ram functioning retained functioning retained retained io ports functioning retained functioning retained register contents are retained, but output is the high-impedance state. irq3 to irq0 functioning functioni ng functioning functioning functioning external interrupts wkp5 to wkp0 functioning functioning functi oning functioning functioning rtc functioning functioning functioning if the timekeeping time-base function is selected, and retained if not selected peripheral functions timer v functioning functioning reset reset reset watchdog timer functioning functioning retained (functioning if the internal oscillator is selected as a count clock * ) sci3, sci3_2 functioning functioning reset reset reset iic2 functioning functioning retained * retained retained timer b1 functioning functioning retained * retained retained timer z functioning functioning retained (the counter increments according to subclocks if the internal clock ( ) is selected as a count clock * ) a/d converter functioning functioning reset reset reset lvd functioning functioning func tioning functioning functioning note: * registers can be read or written in subactive mode.
section 6 power-down modes rev. 3.00 sep. 10, 2007 page 103 of 528 rej09b0216-0300 6.2.1 sleep mode in sleep mode, cpu operation is halted but the on-chip peripheral modules function at the clock frequency set by the ma2, ma1, and ma0 bits in syscr2. cpu register contents are retained. when an interrupt is requested, sleep mode is cleared and interrupt exception handling starts. sleep mode is not cleared if the i bit of the condition code register (ccr) is set to 1 or the requested interrupt is disabled in the interrupt enable register. after sleep mode is cleared, a transition is made to active mode when the lson b it in syscr2 is 0, and a transition is made to subactive mode when the bit is 1. when the res pin goes low, the cpu goes into the re set state and sleep mode is cleared. 6.2.2 standby mode in standby mode, the external clock oscillator is halted, and operation of the cpu and on-chip peripheral modules is halted. however, as long as the rated voltage is supplied, the contents of cpu registers, on-chip ram, and some on-chip peripheral module registers are retained. on-chip ram contents will be retained as long as the vo ltage set by the ram data retention voltage is provided. the i/o ports go to the high-impedance state. standby mode is cleared by an interrupt. when an interrupt is requested, the on-chip oscillator starts functioning. the external oscillator also starts functioning when used. after the time set by the sts2 to sts0 bits in syscr1 has elapsed, standby mode is cleared and the cpu starts interrupt exception handling. standby mode is not cleared if the i bit in the condition code register (ccr) is set to 1 or the requested interrupt is disabled by the interrupt enable bit. when the res pin is driven low in standby mode, the on-chip oscillator starts functioning. once the oscillator starts, the system clock is supplied to the entire chip. the res pin must be kept low for the rated period set by the power-on reset circuit, until the oscillator stabilizes. if the res pin is driven high after the oscillator has stabilized, the internal reset signal is cleared and the cpu starts reset exception handling.
section 6 power-down modes rev. 3.00 sep. 10, 2007 page 104 of 528 rej09b0216-0300 6.2.3 subsleep mode in subsleep mode, operation of the cpu and on-chip peripheral modules other than rtc is halted. as long as a required voltage is applied, the contents of cpu registers, the on-chip ram, and some registers of the on-chip peripheral modules are retained. i/o ports keep the same states as before the transition. subsleep mode is cleared by an interrupt. when an interrupt is requested, subsleep mode is cleared and interrupt exception handling starts. subsleep mode is not cleared if the i bit of ccr is set to 1 or the requested interrupt is disabled in the interrupt enable register. after subsleep mode is cleared, a transition is made to active mode when the lson bit in syscr2 is 0, and a transition is made to subactive mode when the bit is 1. after the time set in bits sts2 to sts0 in syscr1 has elapsed, a transition is made to active mode. when the res pin is driven low in standby mode, the on-chip oscillator starts functioning. once the oscillator starts, the system clock is supplied to the entire chip. the res pin must be kept low for the rated period set by the power-on reset circuit, until the oscillator stabilizes. if the res pin is driven high after the oscillator has stabilized, the internal reset signal is cleared and the cpu starts reset exception handling. 6.2.4 subactive mode the operating frequency of subactive mode is selected from w /2, w /4, and w /8 by the sa1 and sa0 bits in syscr2. after the sleep instruction is executed, the operating frequency changes to the frequency which is set before the execution. when the sleep instruction is ex ecuted in subactive mode, a tran sition to sleep mode, subsleep mode, standby mode, active mode, or subactive m ode is made, depending on the combination of syscr1 and syscr2. when the res pin is driven low in standby mode, the on-chip oscillator starts functioning. once the oscillator starts, the system clock is supplied to the entire chip. the res pin must be kept low for the rated period set by the power-on reset circuit, until the oscillator stabilizes. if the res pin is driven high after the oscillator has stabilized, the internal reset signal is cleared and the cpu starts reset exception handling.
section 6 power-down modes rev. 3.00 sep. 10, 2007 page 105 of 528 rej09b0216-0300 6.3 operating frequenc y in active mode operation in active mode is clocked at the frequency designated by the ma2, ma1, and ma0 bits in syscr2. the operating frequency changes to the set frequency afte r sleep instruction execution. 6.4 direct transition the cpu can execute programs in tw o modes: active and subactive modes. a direct transition is a transition between these two modes without stopping program execution. a direct transition can be made by executing a sleep instruction while the dton bit in syscr2 is set to 1. the direct transition also enables operating frequency modification in active or subactive mode. after the mode transition, direct transition interrupt exception handling starts. if the direct transition interrupt is disabled in interrupt enable register 1, a transition is made instead to sleep or subsleep mode . note that if a direct transition is attempted while the i bit in ccr is set to 1, sleep or subsleep mode will be entered, and the resulting mode cannot be cleared by means of an interrupt. 6.4.1 direct transition from active mode to subactive mode the time from the start of sleep instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (1). direct transition time = {(number of sleep instru ction execution states) + (number of internal processing states)} (tcyc before transition) + (number of interrupt exception handling states) (tsubcyc after transition) (1) example direct transition time = (2 + 1) tosc + 14 8tw = 3tosc + 112tw (when the cpu operating clock of osc w /8 is selected) legend tosc: osc clock cycle time tw: watch clock cycle time tcyc: system clock ( ) cycle time tsubcyc: subclock ( sub ) cycle time
section 6 power-down modes rev. 3.00 sep. 10, 2007 page 106 of 528 rej09b0216-0300 6.4.2 direct transition from su bactive mode to active mode the time from the start of sleep instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (2). direct transition time = {(number of sleep instru ction execution states) + (number of internal processing states)} (tsubcyc before transition) + {(waiting time set in bits sts2 to sts0) + (number of interrupt exception handling states)} (tcyc after transition) (2) example direct transition time = (2 + 1) 8tw + (8192 + 14) tosc = 24tw + 8206tosc (when the cpu operating clock of w /8 osc and a waiting time of 8192 states are selected) legend tosc: osc clock cycle time tw: watch clock cycle time tcyc: system clock ( ) cycle time tsubcyc: subclock ( sub ) cycle time 6.5 module standby function the module-standby function can be set to any peripheral module. in module standby mode, the clock supply to modules stops to enter the pow er-down mode. module standby mode enables each on-chip peripheral module to enter the standby state by setting a bit that corresponds to each module to 1 and cancels the mode by clearing the bit to 0.
section 7 rom rom3560a_000120030300 rev. 3.00 sep. 10, 2007 page 107 of 528 rej09b0216-0300 section 7 rom the features of the flash memory built into this lsi are summarized below. ? programming/erase methods ? the flash memory is programmed 128 bytes at a time. erase is performed in single-block units. to erase the entire flash memory, each block must be erased in turn. ? reprogramming capability ? the flash memory can be reprogrammed up to 1,000 times (min.). ? on-board programming ? on-board programming/erasing can be done in boot mode, in which the boot program built into the chip is started to erase or program of the entire flash memory. in normal user program mode, individual blocks can be erased or programmed. ? programmer mode ? flash memory can be programmed/erased in programmer mode using a prom programmer, as well as in on-board programming mode. ? automatic bit rate adjustment ? for data transfer in boot mode, this lsi's bit rate can be automatically adjusted to match the transfer bit rate of the host. ? programming/erasing protection ? sets software protection against flash memory programming/erasing. ? power-down mode ? operation of the power supply circuit can be partly halted in subactive mode. as a result, flash memory can be read with low power consumption. 7.1 block configuration figure 7.1 shows the block configuration of flas h memory of each product model. the thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. erasing is performed in erasing units shown in these figures. programming is performed in 128- byte units starting from an address with lower eight bits h'00 or h'80.
section 7 rom rev. 3.00 sep. 10, 2007 page 108 of 528 rej09b0216-0300 h8/36079gf h8/36079lf h'000000 h'000001 h'000002 h'000380 h'000381 h'000382 h'000400 h'000401 h'000402 h'000780 h'000781 h'000782 h'000800 h'000801 h'000802 h'000b80 h'000b81 h'000b82 h'000c00 h'000c01 h'000c02 h'000f80 h'000f81 h'000f82 h'001000 h'001001 h'001002 h'00007f h'0003ff h'00047f h'0007ff h'00087f h'000bff h'000c7f h'000fff h'00107f h'007f80 h'007f81 h'007f82 h'007fff h'008000 h'008001 h'008002 h'00ff80 h'00ff81 h'00ff82 h'010000 h'010001 h'010002 h'00807f h'00ffff h'01007f erase unit: 1 kbyte erase unit: 1 kbyte erase unit: 1 kbyte erase unit: 1 kbyte erase unit : 28 kbytes erase unit: 32 kbytes h'017f80 h'017f81 h'017f82 h'018000 h'018001 h'018002 h'017fff h'01807f erase unit: 32 kbytes h'01ff80 h'01ff81 h'01ff82 h'01ffff erase unit: 32 kbytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes figure 7.1 flash memory block configuration (1) (h8/36079gf and h8/36079lf)
section 7 rom rev. 3.00 sep. 10, 2007 page 109 of 528 rej09b0216-0300 h8/36078gf h8/36078lf h'000000 h'000001 h'000002 h'000380 h'000381 h'000382 h'000400 h'000401 h'000402 h'000780 h'000781 h'000782 h'000800 h'000801 h'000802 h'000b80 h'000b81 h'000b82 h'000c00 h'000c01 h'000c02 h'000f80 h'000f81 h'000f82 h'001000 h'001001 h'001002 h'00007f h'0003ff h'00047f h'0007ff h'00087f h'000bff h'000c7f h'000fff h'00107f h'007f80 h'007f81 h'007f82 h'007fff h'008000 h'008001 h'008002 h'00ff80 h'00ff81 h'00ff82 h'010000 h'010001 h'010002 h'00807f h'00ffff h'01007f erase unit: 1 kbyte erase unit: 1 kbyte erase unit: 1 kbyte erase unit: 1 kbyte erase unit: 28 kbytes erase unit: 32 kbytes h'017f80 h'017f81 h'017f82 h'017fff erase unit: 32 kbytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes figure 7.1 flash memory block configuration (2) (h8/36078gf and h8/36078lf)
section 7 rom rev. 3.00 sep. 10, 2007 page 110 of 528 rej09b0216-0300 h8/36077gf h8/36077lf h'0000 h'0001 h'0002 h'0380 h'0381 h'0382 h'0400 h'0401 h'0402 h'0780 h'0781 h'0782 h'0800 h'0801 h'0802 h'0b80 h'0b81 h'0b82 h'0c00 h'0c01 h'0c02 h'0f80 h'0f81 h'0f82 h'1000 h'1001 h'1002 h'007f h'03ff h'047f h'07ff h'087f h'0bff h'0c7f h'0fff h'107f h'7f80 h'7f81 h'7f82 h'7fff h'8000 h'8001 h'8002 h'bf80 h'bf81 h'bf82 h'c000 h'c001 h'c002 h'807f h'bfff h'c07f h'df80 h'df81 h'df82 h'dfff erase unit: 1 kbyte erase unit: 1 kbytes erase unit: 1 kbytes erase unit: 1 kbytes erase unit: 28 kbytes erase unit: 16 kbytes erase unit: 8 kbytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes figure 7.1 flash memory block configuration (3) (h8/36077gf and h8/36077lf)
section 7 rom rev. 3.00 sep. 10, 2007 page 111 of 528 rej09b0216-0300 erase unit: 1 kbyte h8/36074gf h8/36074lf h'0000 h'0001 h'0002 h'0380 h'0381 h'0382 h'0400 h'0401 h'0402 h'0780 h'0781 h'0782 h'0800 h'0801 h'0802 h'0b80 h'0b81 h'0b82 h'0c00 h'0c01 h'0c02 h'0f80 h'0f81 h'0f82 h'1000 h'1001 h'1002 h'007f h'03ff h'047f h'07ff h'087f h'0bff h'0c7f h'0fff h'107f h'7f80 h'7f81 h'7f82 h'7fff erase unit: 1 kbyte erase unit: 1 kbyte erase unit: 1 kbyte erase unit: 28 kbytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes figure 7.1 flash memory block configuration (4) (h8/36074gf and h8/36074lf)
section 7 rom rev. 3.00 sep. 10, 2007 page 112 of 528 rej09b0216-0300 7.2 register descriptions the flash memory has the following registers. ? flash memory control register 1 (flmcr1) ? flash memory control register 2 (flmcr2) ? erase block register 1 (ebr1) ? flash memory power control register (flpwcr) ? flash memory enable register (fenr) 7.2.1 flash memory control register 1 (flmcr1) flmcr1 is a register that makes the flash memory change to program mode, program-verify mode, erase mode, or erase-verify mode. for details on register setting, refer to section 7.4, flash memory programming/erasing. bit bit name initial value r/w description 7 ? 0 ? reserved this bit is always read as 0. 6 swe 0 r/w software write enable when this bit is set to 1, flash memory programming/erasing is enabled. when this bit is cleared to 0, other flmcr1 register bits and all ebr1 bits cannot be set. 5 esu 0 r/w erase setup when this bit is set to 1, the flash memory changes to the erase setup state. when it is cleared to 0, the erase setup state is cancelled. set this bit to 1 before setting the e bit to 1 in flmcr1. 4 psu 0 r/w program setup when this bit is set to 1, the flash memory changes to the program setup state. when it is cleared to 0, the program setup state is cancelled. set this bit to 1 before setting the p bit in flmcr1.
section 7 rom rev. 3.00 sep. 10, 2007 page 113 of 528 rej09b0216-0300 bit bit name initial value r/w description 3 ev 0 r/w erase-verify when this bit is set to 1, the flash memory changes to erase-verify mode. when it is cleared to 0, erase-verify mode is cancelled. 2 pv 0 r/w program-verify when this bit is set to 1, the flash memory changes to program-verify mode. when it is cleared to 0, program- verify mode is cancelled. 1 e 0 r/w erase when this bit is set to 1 while swe=1 and esu=1, the flash memory changes to erase mode. when it is cleared to 0, erase mode is cancelled. 0 p 0 r/w program when this bit is set to 1 while swe=1 and psu=1, the flash memory changes to program mode. when it is cleared to 0, program mode is cancelled. 7.2.2 flash memory control register 2 (flmcr2) flmcr2 is a register that displays the state of flash memory programming/erasing. flmcr2 is a read-only register, and should not be written to. bit bit name initial value r/w description 7 fler 0 r flash memory error indicates that an error has occurred during an operation on flash memory (programming or erasing). when fler is set to 1, flash memory goes to the error-protection state. see section 7.5.3, error protection, for details. 6 to 0 ? all 0 ? reserved these bits are always read as 0.
section 7 rom rev. 3.00 sep. 10, 2007 page 114 of 528 rej09b0216-0300 7.2.3 erase block register 1 (ebr1) ebr1 specifies the flash memory erase area block. ebr1 is initialized to h'00 when the swe bit in flmcr1 is 0. do not set more than one bit at a time, as this will cause all the bits in ebr1 to be automatically cleared to 0. (1) h8/36079gf and h8/36079lf bit bit name initial value r/w description 7 eb7 0 r/w when this bit is set to 1, 32 kbytes of h'018000 to h'01ffff will be erased. 6 eb6 0 r/w when this bit is set to 1, 32 kbytes of h'010000 to h'017fff will be erased. 5 eb5 0 r/w when this bit is set to 1, h'008000 to h'00ffff 32 kbytes of h'010000 to h'017fff will be erased. 4 eb4 0 r/w when this bit is set to 1, 28 kbytes of h'001000 to h'007fff will be erased. 3 eb3 0 r/w when this bit is set to 1, 1 kbyte of h'000c00 to h'000fff will be erased. 2 eb2 0 r/w when this bit is set to 1, 1 kbyte of h'000800 to h'000bff will be erased. 1 eb1 0 r/w when this bit is set to 1, 1 kbyte of h'000400 to h'0007ff will be erased. 0 eb0 0 r/w when this bit is set to 1, 1 kbyte of h'000000 to h'0003ff will be erased. (2) h8/36078gf and h8/36078lf bit bit name initial value r/w description 7 ? 0 ? reserved. although this bit is readable/writable, do not set this bit to 1. 6 eb6 0 r/w when this bit is set to 1, 32 kbytes of h'010000 to h'017fff will be erased. 5 eb5 0 r/w when this bit is set to 1, 32 kbytes of h'008000 to h'00ffff will be erased. 4 eb4 0 r/w when this bit is set to 1, 28 kbytes of h'001000 to h'007fff will be erased. 3 eb3 0 r/w when this bit is set to 1, 1 kbyte of h'000c00 to h'000fff will be erased. 2 eb2 0 r/w when this bit is set to 1, 1 kbyte of h'000800 to h'000bff will be erased. 1 eb1 0 r/w when this bit is set to 1, 1 kbyte of h'000400 to h'0007ff will be erased. 0 eb0 0 r/w when this bit is set to 1, 1 kbyte of h'000000 to h'0003ff will be erased.
section 7 rom rev. 3.00 sep. 10, 2007 page 115 of 528 rej09b0216-0300 (3) h8/36077gf and h8/36077lf bit bit name initial value r/w description 7 ? 0 ? reserved. this bit is always read as 0. 6 eb6 0 r/w when this bit is set to 1, 8 kbytes of h'c000 to h'dfff will be erased. 5 eb5 0 r/w when this bit is set to 1, 16 kbytes of h'8000 to h'bfff will be erased. 4 eb4 0 r/w when this bit is set to 1, 28 kbytes of h'1000 to h'7fff will be erased. 3 eb3 0 r/w when this bit is set to 1, 1 kbyte of h'0c00 to h'0fff will be erased. 2 eb2 0 r/w when this bit is set to 1, 1 kbyte of h'0800 to h'0bff will be erased. 1 eb1 0 r/w when this bit is set to 1, 1 kbyte of h'0400 to h'07ff will be erased. 0 eb0 0 r/w when this bit is set to 1, 1 kbyte of h'0000 to h'03ff will be erased. (4) h8/36074gf and h8/36074lf bit bit name initial value r/w description 7 ? 0 ? reserved. this bit is always read as 0. 6 ? 0 ? reserved. although this bit is readable/writable, do not set this bit to 1. 5 ? 0 ? reserved. although this bit is readable/writable, do not set this bit to 1. 4 eb4 0 r/w when this bit is set to 1, 28 kbytes of h'1000 to h'7fff will be erased. 3 eb3 0 r/w when this bit is set to 1, 1 kbyte of h'0c00 to h'0fff will be erased. 2 eb2 0 r/w when this bit is set to 1, 1 kbyte of h'0800 to h'0bff will be erased. 1 eb1 0 r/w when this bit is set to 1, 1 kbyte of h'0400 to h'07ff will be erased. 0 eb0 0 r/w when this bit is set to 1, 1 kbyte of h'0000 to h'03ff will be erased.
section 7 rom rev. 3.00 sep. 10, 2007 page 116 of 528 rej09b0216-0300 7.2.4 flash memory power control register (flpwcr) flpwcr enables or disables a transition to the flash memory power-down mode when the lsi switches to subactive mode. there are two modes: mode in which operation of the power supply circuit of flash memory is partly halted in power-down mode and flash memory can be read, and mode in which even if a transition is made to subactive mode, operation of the power supply circuit of flash memory is retain ed and flash memory can be read. bit bit name initial value r/w description 7 pdwnd 0 r/w power-down disable when this bit is 0 and a transition is made to subactive mode, the flash memory enters the power-down mode. when this bit is 1, the flash memory remains in the normal mode even after a transition is made to subactive mode. 6 to 0 ? all 0 ? reserved these bits are always read as 0. 7.2.5 flash memory enable register (fenr) bit 7 (flshe) in fenr enables or disables the cpu access to the flash memory control registers, flmcr1, flmcr2, ebr1, and flpwcr. bit bit name initial value r/w description 7 flshe 0 r/w flash memory control register enable flash memory control registers can be accessed when this bit is set to 1. flash memory control registers cannot be accessed when this bit is set to 0. 6 to 0 ? all 0 ? reserved these bits are always read as 0.
section 7 rom rev. 3.00 sep. 10, 2007 page 117 of 528 rej09b0216-0300 7.3 on-board programming modes there are two modes for programming/erasing of the flash memory; boot mode, which enables on- board programming/erasing, and programmer mode , in which programming/erasing is performed with a prom programmer. on-board programming/erasing can also be performed in user program mode. at reset-start in reset mode, this lsi changes to a mode depending on the test pin settings, nmi pin settings, and input level of each port, as shown in table 7.1. the input level of each pin must be defined four states before the reset ends. when changing to boot mode, the boot program bu ilt into this lsi is in itiated. the boot program transfers the programming control program from the externally connected host to on-chip ram via sci3. after erasing the entire flash memory, the programming control program is executed. this can be used for programming initial values in the on-board state or for a forcible return when programming/erasing can no longer be done in user program mode. in user program mode, individual blocks can be erased and programmed by branching to the user program/erase control program prepared by the user. table 7.1 setting programming modes test nmi p85 pb0 pb1 pb2 lsi state after reset end 0 1 x x x x user mode 0 0 1 x x x boot mode 1 x x 0 0 0 programmer mode [legend] x: don't care. 7.3.1 boot mode table 7.2 shows the boot mode operations between reset end and branching to the programming control program. 1. when boot mode is used, the flash memory programming control program must be prepared in the host beforehand. prepare a programming control program in accordance with the description in section 7.4, flash memory programming/erasing. 2. sci3 should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop bit, and no parity. 3. when the boot program is initiated, the chip measures the low-level period of asynchronous sci communication data (h'00) transmitted continuously from the host. the chip then calculates the bit rate of transmission from the host, and adjusts the sci3 bit rate to match that of the host. the reset should end with the rxd pin high. the rxd and txd pins should be
section 7 rom rev. 3.00 sep. 10, 2007 page 118 of 528 rej09b0216-0300 pulled up on the board if necessary. after the reset is complete, it takes approximately 100 states before the chip is ready to measure the low-level period. 4. after matching the bit rates, the chip transmits one h'00 byte to the host to indicate the completion of bit rate adjustment. the host should confirm that this adjustment end indication (h'00) has been received normally, and transmit one h'55 byte to the chip. if reception could not be performed normally, initiate boot mode again by a reset. depending on the host's transfer bit rate and system clock frequency of this lsi, there will be a discrepancy between the bit rates of the host and the chip. to operate the sci properly, set the host's transfer bit rate and system clock frequency of this lsi within the ranges listed in table 7.3. 5. in boot mode, a part of the on-chip ram area is used by the boot program. the area h'fff780 to h'fffeef for microcontrollers supporting advanced mode or h'f780 to h'feef for microcontrollers supporting normal mode, is the area to which the programming control program is transferred from the host. the boot program area cannot be used until the execution state in boot mode switches to the programming control program. 6. before branching to the programming control program, the chip terminates transfer operations by sci3 (by clearing the re and te bits in scr to 0), however the adjusted bit rate value remains set in brr. therefore, the programming control program can still use it for transfer of program data or verify data with the host. the txd pin is high (pcr22 = 1, p22 = 1). the contents of the cpu general registers are undefined immediately after branching to the programming control program. these registers must be initialized at the beginning of the programming control program, as the stack pointer (sp), in particular, is used implicitly in subroutine calls, etc. 7. boot mode can be cleared by a reset. end the reset after driving the reset pin low, waiting at least 20 states, and then setting the nmi pin. boot mode is also cleared when a wdt overflow occurs. 8. do not change the test pin and nmi pin input levels in boot mode.
section 7 rom rev. 3.00 sep. 10, 2007 page 119 of 528 rej09b0216-0300 table 7.2 boot mode operation communication contents processing contents host operation lsi operation processing contents continuously transmits data h'00 at specified bit rate. branches to boot program at reset-start. boot program initiation h'00, h'00 . . . h'00 h'00 h'55 transmits data h'55 when data h'00 is received error-free. h'xx transmits number of bytes (n) of programming control program to be transferred as 2-byte data (low-order byte following high-order byte) transmits 1-byte of programming control program (repeated for n times) h'aa reception h'aa reception upper bytes, lower bytes echoback echoback h'aa h'aa branches to programming control program transferred to on-chip ram and starts execution. transmits data h'aa to host. checks flash memory data, erases all flash memory blocks in case of written data existing, and transmits data h'aa to host. (if erase could not be done, transmits data h'ff to host and aborts operation.) h'ff boot program erase error item boot mode initiation measures low-level period of receive data h'00. calculates bit rate and sets brr in sci3. transmits data h'00 to host as adjustment end indication. h'55 reception. bit rate adjustment echobacks the 2-byte data received to host. echobacks received data to host and also transfers it to ram. (repeated for n times) transfer of number of bytes of programming control program flash memory erase
section 7 rom rev. 3.00 sep. 10, 2007 page 120 of 528 rej09b0216-0300 table 7.3 system clock frequencies for which automatic adjustment of lsi bit rate is possible host bit rate system clock frequency range of lsi 9,600 bps 4,800 bps 10 mhz 7.3.2 programming/erasing in user program mode on-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program. the user must set branching conditions and provide on-board means of supplying programming data. the flash memory must contain the user program/erase control program or a program that provides the user program/erase control program from external memory. as the flash memory itself cannot be read during programming/erasing, transfer the user program/erase control program to on-chip ram, as in boot mode. figure 7.2 shows a sample procedure for programming/erasing in user program mode. prepare a user program/erase control program in accordance with the description in section 7.4, flash memory programming/erasing. ye s no program/erase? transfer user program/erase control program to ram reset-start branch to user program/erase control program in ram execute user program/erase control program (flash memory rewrite) branch to flash memory application program branch to flash memory application program figure 7.2 programming/erasing flowchart example in user program mode
section 7 rom rev. 3.00 sep. 10, 2007 page 121 of 528 rej09b0216-0300 7.4 flash memory programming/erasing a software method using the cpu is employed to program and erase flash memory in the on- board programming modes. depending on the flmcr1 setting, the flash memory operates in one of the following four modes: program mode, program-verify mode, erase mode, and erase-verify mode. the programming control program in boot mode and the user program/erase control program in user program mode use these operating modes in combination to perform programming/erasing. flash memory programming and erasing should be performed in accordance with the descriptions in section 7.4. 1, program/program-verify and section 7.4.2, erase/erase-verify, respectively. 7.4.1 program/program-verify when writing data or programs to the flash memory, the program/program-verify flowchart shown in figure 7.3 should be followed. performing programming operations according to this flowchart will enable data or programs to be written to the flash memory without subjecting the chip to voltage stress or sacrificing program data reliability. 1. programming must be done to an empty address. do not reprogram an address to which programming has already been performed. 2. programming should be carried out 128 bytes at a time. a 128-byte data transfer must be performed even if writing fewer than 128 bytes. in this case, h'ff data must be written to the extra addresses. 3. prepare the following data storage areas in ram: a 128-byte programming data area, a 128- byte reprogramming data area, and a 128-byte additional-programming data area. perform reprogramming data computation according to table 7.4, and additional programming data computation according to table 7.5. 4. consecutively transfer 128 bytes of data in byte units from the reprogramming data area or additional-programming data area to the flash memory. the program address and 128-byte data are latched in the flash memory. the lower 8 bits of the start address in the flash memory destination area must be h'00 or h'80. 5. the time during which the p bit is set to 1 is the programming time. table 7.6 shows the allowable programming times. 6. the watchdog timer (wdt) is set to prevent overprogramming due to program runaway, etc. an overflow cycle of approximately 6.6 ms is allowed. 7. for a dummy write to a verify address, write 1-byte data h'ff to an address whose lower 2 bits are b'00. verify data can be read in words or in longwords from the address to which a dummy write was performed.
section 7 rom rev. 3.00 sep. 10, 2007 page 122 of 528 rej09b0216-0300 8. the maximum number of repetitions of the program/program-verify sequence of the same bit is 1,000. start end of programming note: * the rts instruction must not be used during the following 1. and 2. periods. 1. a period between 128-byte data programming to flash memory and the p bit clearing 2. a period between dummy writing of h'ff to a verify address and verify data reading set swe bit in flmcr1 write pulse application subroutine wait 1 s apply write pulse * end sub set psu bit in flmcr1 wdt enable disable wdt wait 50 s set p bit in flmcr1 wait (wait time=programming time) clear p bit in flmcr1 wait 5 s clear psu bit in flmcr1 wait 5 s n= 1 m= 0 no no no yes yes yes yes wait 4 s wait 2 s wait 2 s apply write pulse set pv bit in flmcr1 set block start address as verify address h'ff dummy write to verify address read verify data verify data = write data? reprogram data computation additional-programming data computation clear pv bit in flmcr1 clear swe bit in flmcr1 m = 1 m= 0 ? increment address programming failure no clear swe bit in flmcr1 wait 100 s no yes n 6? no yes n 6 ? wait 100 s n 1000 ? n n + 1 write 128-byte data in ram reprogram data area consecutively to flash memory store 128-byte program data in program data area and reprogram data area apply write pulse sub-routine-call 128-byte data verification completed? successively write 128-byte data from additional- programming data area in ram to flash memory * figure 7.3 program/program-verify flowchart
section 7 rom rev. 3.00 sep. 10, 2007 page 123 of 528 rej09b0216-0300 table 7.4 reprogram data computation table program data verify data reprogram data comments 0 0 1 programming completed 0 1 0 reprogram bit 1 0 1 ? 1 1 1 remains in erased state table 7.5 additional-program data computation table reprogram data verify data additional-program data comments 0 0 0 additional-program bit 0 1 1 no additional programming 1 0 1 no additional programming 1 1 1 no additional programming table 7.6 programming time n (number of writes) programming time in additional programming comments 1 to 6 30 10 7 to 1,000 200 ? note: time shown in s.
section 7 rom rev. 3.00 sep. 10, 2007 page 124 of 528 rej09b0216-0300 7.4.2 erase/erase-verify when erasing flash memory, the erase/erase-veri fy flowchart shown in figure 7.4 should be followed. 1. prewriting (setting erase block data to all 0s) is not necessary. 2. erasing is performed in block units. make only a single-bit specification in the erase block register (ebr1). to erase multiple bloc ks, each block must be erased in turn. 3. the time during which the e bit is set to 1 is the flash memory erase time. 4. the watchdog timer (wdt) is set to prevent overerasing due to program runaway, etc. an overflow cycle of approximately 19.8 ms is allowed. 5. for a dummy write to a verify address, write 1-byte data h'ff to an address whose lower two bits are b'00. verify data can be read in longwords from the address to which a dummy write was performed. 6. if the read data is not erased successfully, se t erase mode again, and repeat the erase/erase- verify sequence as before. the maximum number of repetitions of the erase/erase-verify sequence is 100. 7.4.3 interrupt handling when programming/erasing flash memory all interrupts, including the nmi interrupt, are disabled while flash memory is being programmed or erased, or while the boot program is executing, for the following three reasons: 1. interrupt during programming/erasing may cause a violation of the programming or erasing algorithm, with the result that normal operation cannot be assured. 2. if interrupt exception handling starts before the vector address is written or during programming/erasing, a correct vector cannot be fetched and the cpu malfunctions. 3. if an interrupt occurs during boot program execution, normal boot mode sequence cannot be carried out.
section 7 rom rev. 3.00 sep. 10, 2007 page 125 of 528 rej09b0216-0300 erase start set ebr1 enable wdt wait 1 s wait 100 s swe bit 1 n 1 esu bit 1 e bit 1 wait 10 ms e bit 0 wait 10 s esu bit 10 10 s disable wdt read verify data increment address verify data + all 1s ? last address of block ? all erase block erased ? set block start address as verify address h'ff dummy write to verify address wait 20 s wait 2 s ev bit 1 wait 100 s end of erasing note: * the rts instruction must not be used during a period between dummy writing of h'ff to a verify address and verify data reading. swe bit 0 wait 4 s ev bit 0 n 100 ? wait 100 s erase failure swe bit 0 wait 4 s ev bit 0 n n + 1 ye s no ye s ye s ye s ye s no no no * figure 7.4 erase/erase-verify flowchart
section 7 rom rev. 3.00 sep. 10, 2007 page 126 of 528 rej09b0216-0300 7.5 program/erase protection there are three kinds of flash memory program/er ase protection; hardware protection, software protection, and error protection. 7.5.1 hardware protection hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset, subactive mode, subsleep mode, or standby mode. flash memory control register 1 (flmcr1), flash memory control register 2 (flmcr2), and erase block register 1 (ebr1) are initialized. in a reset via the res pin, the reset state is not entered unless the res pin is held low until oscillation stabilizes after powering on. in the case of a reset during operation, hold the res pin low for the res pulse width specified in the ac characteristics section. 7.5.2 software protection software protection can be implemented against programming/erasing of all flash memory blocks by clearing the swe bit in flmcr1. when software protection is in effect, setting the p or e bit in flmcr1 does not cause a transition to program mode or erase mode. by setting the erase block register 1 (ebr1), erase protection can be set for individual blocks. when ebr1 is set to h'00, erase protection is set for all blocks. 7.5.3 error protection in error protection, an error is detected when cpu runaway occurs during flash memory programming/erasing, or operati on is not performed in accordance with the program/erase algorithm, and the program/erase operation is forcibly aborted. aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. when the following errors are detected during programming/erasing of flash memory, the fler bit in flmcr2 is set to 1, and the error protection state is entered. ? when the flash memory of the relevant address area is read during programming/erasing (including vector read and instruction fetch) ? immediately after exception handling excluding a reset during programming/erasing ? when a sleep instruction is executed during programming/erasing
section 7 rom rev. 3.00 sep. 10, 2007 page 127 of 528 rej09b0216-0300 the flmcr1, flmcr2, and ebr1 settings are retained, however program mode or erase mode is aborted at the point at which the error occu rred. program mode or erase mode cannot be re- entered by re-setting the p or e bit. however, pv and ev bit settings are retained, and a transition can be made to verify mode. error protection can be cleared only by a reset. 7.6 programmer mode in programmer mode, a prom programmer can be used to perform programming/erasing via a socket adapter, just as a discrete flash memo ry. use a prom programmer that supports the mcu device type with the on-chip 128-kbyte flash memory (fztat64v5). 7.7 power-down states for flash memory in user mode, the flash memory will operate in either of the following states: ? normal operating mode the flash memory can be read and written to at high speed. ? power-down operating mode the power supply circuit of flash memory can be partly halted. as a result, flash memory can be read with low power consumption. ? standby mode all flash memory circuits are halted. table 7.7 shows the correspondence between the operating modes of this lsi and the flash memory. in subactive mode, the flash memory can be set to operate in power-down mode with the pdwnd bit in flpwcr. when the flash memory returns to its normal operating state from power-down mode or standby mode , a period to stabilize operation of the power supply circuits that were stopped is needed. when the flash memory returns to its normal operating state, bits sts2 to sts0 in syscr1 must be set to provide a wait time of at least 20 s, even when the external clock is being used.
section 7 rom rev. 3.00 sep. 10, 2007 page 128 of 528 rej09b0216-0300 table 7.7 flash memory operating states flash memory operating state lsi operating state pdwnd = 0 (initial value) pdwnd = 1 active mode normal operating mode normal operating mode subactive mode power-down mode normal operating mode sleep mode normal operating mode normal operating mode subsleep mode standby mode standby mode standby mode standby mode standby mode
section 8 ram ram0500a_000120030300 rev. 3.00 sep. 10, 2007 page 129 of 528 rej09b0216-0300 section 8 ram microcontrollers of the h8/36079 group and h8/36077 group have an on-chip high-speed static ram. the ram is connected to the cpu by a 16 -bit data bus, enabling two-state access by the cpu to both byte data and word data. product classification ram size ram address 5.0-v specification h8/36079gf 3.3-v specification h8/36079lf 5.0-v specification h8/36078gf h8/36079 group 3.3-v specification h8/36078lf 6 kbytes h'ffe000 to h'ffefff, h'fff780 to h'ffff7f * 1 5.0-v specification h8/36077gf 3.3-v specification h8/36077lf 5.0-v specification h8/36074gf flash memory version (f-ztat version) h8/36077 group 3.3-v specification h8/36074lf 4 kbytes h'e800 to h'efff, h'f780 to h'ff7f * 2 notes: 1. when the e7 or e8 is used, area h'fff780 to h'fffb7f must not be accessed. 2. when the e7 or e8 is used, area h'f780 to h'fb7f must not be accessed.
section 8 ram rev. 3.00 sep. 10, 2007 page 130 of 528 rej09b0216-0300
section 9 i/o ports rev. 3.00 sep. 10, 2007 page 131 of 528 rej09b0216-0300 section 9 i/o ports this lsi has 47 general i/o ports and 8 general input-only ports. port 6 is a large current port, which can drive 20 ma (@v ol = 1.5 v) when a low level signal is output. any of these ports can become an input port immediately after a reset. they can also be used as i/o pins of the on-chip peripheral modules or external interrupt input pins, and these functions can be switched depending on the register settings. the registers for selecting these functions can be divided into two types: those included in i/o ports and those included in each on-chip peripheral module. general i/o ports are comprised of the port control register for controlling inputs/outputs and the port data register for storing output data and can select inputs/outputs in bit units. for functions in each port, see appendix b.1, i/o port block diagrams. fo r the execution of bit- manipulation instructions to the port control register and port data register, see section 2.8.3, bit- manipulation instruction. 9.1 port 1 port 1 is a general i/o port also functioning as irq interrupt input pins, an rtc output pin, a 14- bit pwm output pin, a timer b1 input pin, and a timer v input pin. figure 9.1 shows its pin configuration. p17/ irq3 /trgv p16/ irq2 p15/ irq1 /tmib1 p14/ irq0 p12 p11/pwm p10/tmow port 1 figure 9.1 port 1 pin configuration port 1 has the following registers. ? port mode register 1 (pmr1) ? port control register 1 (pcr1) ? port data register 1 (pdr1) ? port pull-up control register 1 (pucr1)
section 9 i/o ports rev. 3.00 sep. 10, 2007 page 132 of 528 rej09b0216-0300 9.1.1 port mode register 1 (pmr1) pmr1 switches the functions of pins in port 1 and port 2. bit bit name initial value r/w description 7 irq3 0 r/w this bit selects the function of pin p17/ irq3 /trgv. 0: general i/o port 1: irq3 /trgv input pin 6 irq2 0 r/w this bit selects the function of pin p16/ irq2 . 0: general i/o port 1: irq2 input pin 5 irq1 0 r/w this bit selects the function of pin p15/ irq1 /tmib1. 0: general i/o port 1: irq1 /tmib1 input pin 4 irq0 0 r/w this bit selects the function of pin p14/ irq0 . 0: general i/o port 1: irq0 input pin 3 txd2 0 r/w this bit selects the function of pin p72/txd_2. 0: general i/o port 1: txd_2 output pin 2 pwm 0 r/w this bit selects the function of pin p11/pwm. 0: general i/o port 1: pwm output pin 1 txd 0 r/w this bit selects the function of pin p22/txd. 0: general i/o port 1: txd output pin 0 tmow 0 r/w this bit selects the function of pin p10/tmow. 0: general i/o port 1: tmow output pin
section 9 i/o ports rev. 3.00 sep. 10, 2007 page 133 of 528 rej09b0216-0300 9.1.2 port control register 1 (pcr1) pcr1 selects inputs/outputs in bit units for pins to be used as general i/o ports of port 1. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pcr17 pcr16 pcr15 pcr14 ? pcr12 pcr11 pcr10 0 0 0 0 ? 0 0 0 w w w w ? w w w when the corresponding pin is designated in pmr1 as a general i/o pin, setting a pcr1 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. bit 3 is a reserved bit. 9.1.3 port data register 1 (pdr1) pdr1 is a general i/o port data register of port 1. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p17 p16 p15 p14 ? p12 p11 p10 0 0 0 0 1 0 0 0 r/w r/w r/w r/w ? r/w r/w r/w pdr1 stores output data for port 1 pins. if pdr1 is read while pcr1 bits are set to 1, the value stored in pdr1 are read. if pdr1 is read while pcr1 bits are cleared to 0, the pin states are read regardless of the value stored in pdr1. bit 3 is a reserved bit. this bit is always read as 1.
section 9 i/o ports rev. 3.00 sep. 10, 2007 page 134 of 528 rej09b0216-0300 9.1.4 port pull-up control register 1 (pucr1) pucr1 controls the pull-up mos in bit units of the pins set as the input ports. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pucr17 pucr16 pucr15 pucr14 ? pucr12 pucr11 pucr10 0 0 0 0 1 0 0 0 r/w r/w r/w r/w ? r/w r/w r/w only bits for which pcr1 is cleared are valid. the pull-up mos of p17 to p14 and p12 to p10 pins enter the on- state when these bits are set to 1, while they enter the off-state when these bits are cleared to 0. bit 3 is a reserved bit. this bit is always read as 1. 9.1.5 pin functions the correspondence between the register specification and the port functions is shown below. p17/ irq3 /trgv pin register pmr1 pcr1 bit name irq3 pcr17 pin function setting value 0 0 p17 input pin 1 p17 output pin 1 x irq3 input/trgv input pin [legend] x: don't care.
section 9 i/o ports rev. 3.00 sep. 10, 2007 page 135 of 528 rej09b0216-0300 p16/ irq2 pin register pmr1 pcr1 bit name irq2 pcr16 pin function setting value 0 0 p16 input pin 1 p16 output pin 1 x irq2 input pin [legend] x: don't care. p15/ irq1 /tmib1 pin register pmr1 pcr1 bit name irq1 pcr15 pin function setting value 0 0 p15 input pin 1 p15 output pin 1 x irq1 input/tmib1 input pin [legend] x: don't care. p14/ irq0 pin register pmr1 pcr1 bit name irq0 pcr14 pin function setting value 0 0 p14 input pin 1 p14 output pin 1 x irq0 input pin [legend] x: don't care. p12 pin register pcr1 bit name pcr12 pin function 0 p12 input pin setting value 1 p12 output pin
section 9 i/o ports rev. 3.00 sep. 10, 2007 page 136 of 528 rej09b0216-0300 p11/pwm pin register pmr1 pcr1 bit name pwm pcr11 pin function setting value 0 0 p11 input pin 1 p11 output pin 1 x pwm output pin [legend] x: don't care. p10/tmow pin register pmr1 pcr1 bit name tmow pcr10 pin function setting value 0 0 p10 input pin 1 p10 output pin 1 x tmow output pin [legend] x: don't care.
section 9 i/o ports rev. 3.00 sep. 10, 2007 page 137 of 528 rej09b0216-0300 9.2 port 2 port 2 is a general i/o port also functioning as sci3 i/o pins. each pin of the port 2 is shown in figure 9.2. the register settings of pmr1and sci3 have priority for functions of the pins for both uses. p24 p23 p22/txd p21/rxd p20/sck3 port 2 figure 9.2 port 2 pin configuration port 2 has the following registers. ? port control register 2 (pcr2) ? port data register 2 (pdr2) ? port mode register 3 (pmr3) 9.2.1 port control register 2 (pcr2) pcr2 selects inputs/outputs in bit units for pins to be used as general i/o ports of port 2. bit bit name initial value r/w description 7 to 5 ? ? ? reserved 4 3 2 1 0 pcr24 pcr23 pcr22 pcr21 pcr20 0 0 0 0 0 w w w w w when each of the port 2 pins p24 to p20 functions as a general i/o port, setting a pcr2 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port.
section 9 i/o ports rev. 3.00 sep. 10, 2007 page 138 of 528 rej09b0216-0300 9.2.2 port data register 2 (pdr2) pdr2 is a general i/o port data register of port 2. bit bit name initial value r/w description 7 to 5 ? all 1 ? reserved these bits are always read as 1. 4 3 2 1 0 p24 p23 p22 p21 p20 0 0 0 0 0 r/w r/w r/w r/w r/w pdr2 stores output data for port 2 pins. if pdr2 is read while pcr2 bits are set to 1, the value stored in pdr2 is read. if pdr2 is read while pcr2 bits are cleared to 0, the pin states are read regardless of the value stored in pdr2. 9.2.3 port mode register 3 (pmr3) pmr3 selects the cmos output or nmos open-drain output for port 2. bit bit name initial value r/w description 7 to 5 ? all 0 ? reserved these bits are always read as 0. 4 3 pof24 pof23 0 0 r/w r/w when the bit is set to 1, the corresponding pin is cut off by pmos and it functions as the nmos open-drain output. when cleared to 0, the pin functions as the cmos output. 2 to 0 ? all 1 ? reserved these bits are always read as 1.
section 9 i/o ports rev. 3.00 sep. 10, 2007 page 139 of 528 rej09b0216-0300 9.2.4 pin functions the correspondence between the register specification and the port functions is shown below. p24 pin register pcr2 bit name pcr24 pin function setting value 0 p24 input pin 1 p24 output pin p23 pin register pcr2 bit name pcr23 pin function setting value 0 p23 input pin 1 p23 output pin p22/txd pin register pmr1 pcr2 bit name txd pcr22 pin function setting value 0 0 p22 input pin 1 p22 output pin 1 x txd output pin [legend] x: don't care.
section 9 i/o ports rev. 3.00 sep. 10, 2007 page 140 of 528 rej09b0216-0300 p21/rxd pin register scr3 pcr2 bit name re pcr21 pin function setting value 0 0 p21 input pin 1 p21 output pin 1 x rxd input pin [legend] x: don't care. p20/sck3 pin register scr3 smr pcr2 bit name cke1 cke0 com pcr20 pin function setting value 0 0 0 0 p20 input pin 1 p20 output pin 0 0 1 x sck3 output pin 0 1 x x sck3 output pin 1 x x x sck3 input pin [legend] x: don't care.
section 9 i/o ports rev. 3.00 sep. 10, 2007 page 141 of 528 rej09b0216-0300 9.3 port 3 port 3 is a general i/o port. each pin of the port 3 is shown in figure 9.3. p37 p36 p35 p34 p33 p32 p31 p30 port 3 figure 9.3 port 3 pin configuration port 3 has the following registers. ? port control register 3 (pcr3) ? port data register 3 (pdr3) 9.3.1 port control register 3 (pcr3) pcr3 selects inputs/outputs in bit units for pins to be used as general i/o ports of port 3. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pcr37 pcr36 pcr35 pcr34 pcr33 pcr32 pcr31 pcr30 0 0 0 0 0 0 0 0 w w w w w w w w setting a pcr3 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port.
section 9 i/o ports rev. 3.00 sep. 10, 2007 page 142 of 528 rej09b0216-0300 9.3.2 port data register 3 (pdr3) pdr3 is a general i/o port data register of port 3. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p37 p36 p35 p34 p33 p32 p31 p30 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w pdr3 stores output data for port 3 pins. if pdr3 is read while pcr3 bits are set to 1, the value stored in pdr3 is read. if pdr3 is read while pcr3 bits are cleared to 0, the pin states are read regardless of the value stored in pdr3. 9.3.3 pin functions the correspondence between the register specification and the port functions is shown below. p37 pin register pcr3 bit name pcr37 pin function setting value 0 p37 input pin 1 p37 output pin p36 pin register pcr3 bit name pcr36 pin function setting value 0 p36 input pin 1 p36 output pin
section 9 i/o ports rev. 3.00 sep. 10, 2007 page 143 of 528 rej09b0216-0300 p35 pin register pcr3 bit name pcr35 pin function setting value 0 p35 input pin 1 p35 output pin p34 pin register pcr3 bit name pcr34 pin function setting value 0 p34 input pin 1 p34 output pin p33 pin register pcr3 bit name pcr33 pin function setting value 0 p33 input pin 1 p33 output pin p32 pin register pcr3 bit name pcr32 pin function setting value 0 p32 input pin 1 p32 output pin
section 9 i/o ports rev. 3.00 sep. 10, 2007 page 144 of 528 rej09b0216-0300 p31 pin register pcr3 bit name pcr31 pin function setting value 0 p31 input pin 1 p31 output pin p30 pin register pcr3 bit name pcr30 pin function setting value 0 p30 input pin 1 p30 output pin
section 9 i/o ports rev. 3.00 sep. 10, 2007 page 145 of 528 rej09b0216-0300 9.4 port 5 port 5 is a general i/o port also functioning as an i 2 c bus interface i/o pin, an a/d trigger input pin, and wakeup interrupt input pin. each pin of the port 5 is shown in figure 9.4. the register setting of the i 2 c bus interface register has priority for functions of the pins p57/scl and p56/sda. since the output buffer for pins p56 and p57 has the nmos push-pull structure, it differs from an output buffer with the cmos structure in the high-level output characteristics (see section 22, electrical characteristics). p57/scl p56/sda p55/ wkp5 / adtr g p54/ wkp4 p53/ wkp3 p52/ wkp2 p51/ wkp1 p50/ wkp0 port 5 figure 9.4 port 5 pin configuration port 5 has the following registers. ? port mode register 5 (pmr5) ? port control register 5 (pcr5) ? port data register 5 (pdr5) ? port pull-up control register 5 (pucr5)
section 9 i/o ports rev. 3.00 sep. 10, 2007 page 146 of 528 rej09b0216-0300 9.4.1 port mode register 5 (pmr5) pmr5 switches the functions of pins in port 5. bit bit name initial value r/w description 7 6 pof57 pof56 0 0 r/w r/w when the bit is set to 1, the corresponding pin is cut off by pmos and it functions as the nmos open-drain output. when cleared to 0, the pin functions as the cmos output. 5 wkp5 0 r/w this bit selects the function of pin p55/ wkp5 / adtrg . 0: general i/o port 1: wkp5 / adtrg input pin 4 wkp4 0 r/w this bit selects the function of pin p54/ wkp4 . 0: general i/o port 1: wkp4 input pin 3 wkp3 0 r/w this bit selects the function of pin p53/ wkp3 . 0: general i/o port 1: wkp3 input pin 2 wkp2 0 r/w this bit selects the function of pin p52/ wkp2 . 0: general i/o port 1: wkp2 input pin 1 wkp1 0 r/w this bit selects the function of pin p51/ wkp1 . 0: general i/o port 1: wkp1 input pin 0 wkp0 0 r/w this bit selects the function of pin p50/ wkp0 . 0: general i/o port 1: wkp0 input pin
section 9 i/o ports rev. 3.00 sep. 10, 2007 page 147 of 528 rej09b0216-0300 9.4.2 port control register 5 (pcr5) pcr5 selects inputs/outputs in bit units for pins to be used as general i/o ports of port 5. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pcr57 pcr56 pcr55 pcr54 pcr53 pcr52 pcr51 pcr50 0 0 0 0 0 0 0 0 w w w w w w w w when each of the port 5 pins p57 to p50 functions as a general i/o port, setting a pcr5 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. 9.4.3 port data register 5 (pdr5) pdr5 is a general i/o port data register of port 5. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p57 p56 p55 p54 p53 p52 p51 p50 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w stores output data for port 5 pins. if pdr5 is read while pcr5 bits are set to 1, the value stored in pdr5 are read. if pdr5 is read while pcr5 bits are cleared to 0, the pin states are read regardless of the value stored in pdr5.
section 9 i/o ports rev. 3.00 sep. 10, 2007 page 148 of 528 rej09b0216-0300 9.4.4 port pull-up control register 5 (pucr5) pucr5 controls the pull-up mos in bit units of the pins set as the input ports. bit bit name initial value r/w description 7, 6 ? all 0 ? reserved these bits are always read as 0. 5 4 3 2 1 0 pucr55 pucr54 pucr53 pucr52 pucr51 pucr50 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w only bits for which pcr5 is cleared are valid. the pull-up mos of the corresponding pins enter the on-state when these bits are set to 1, while they enter the off-state when these bits are cleared to 0. 9.4.5 pin functions the correspondence between the register specification and the port functions is shown below. p57/scl pin register iccr1 pcr5 bit name ice pcr57 pin function setting value 0 0 p57 input pin 1 p57 output pin 1 x scl i/o pin [legend] x: don't care. scl performs the nmos open-drain output, that enables a direct bus drive.
section 9 i/o ports rev. 3.00 sep. 10, 2007 page 149 of 528 rej09b0216-0300 p56/sda pin register iccr1 pcr5 bit name ice pcr56 pin function setting value 0 0 p56 input pin 1 p56 output pin 1 x sda i/o pin [legend] x: don't care. sda performs the nmos open-drain output that enables a direct bus drive. p55/ wkp5 / adtrg pin register pmr5 pcr5 bit name wkp5 pcr55 pin function setting value 0 0 p55 input pin 1 p55 output pin 1 x wkp5 / adtrg input pin [legend] x: don't care. p54/ wkp4 pin register pmr5 pcr5 bit name wkp4 pcr54 pin function setting value 0 0 p54 input pin 1 p54 output pin 1 x wkp4 input pin [legend] x: don't care.
section 9 i/o ports rev. 3.00 sep. 10, 2007 page 150 of 528 rej09b0216-0300 p53/ wkp3 pin register pmr5 pcr5 bit name wkp3 pcr53 pin function setting value 0 0 p53 input pin 1 p53 output pin 1 x wkp3 input pin [legend] x: don't care. p52/ wkp2 pin register pmr5 pcr5 bit name wkp2 pcr52 pin function setting value 0 0 p52 input pin 1 p52 output pin 1 x wkp2 input pin [legend] x: don't care. p51/ wkp1 pin register pmr5 pcr5 bit name wkp1 pcr51 pin function setting value 0 0 p51 input pin 1 p51 output pin 1 x wkp1 input pin [legend] x: don't care. p50/ wkp0 pin register pmr5 pcr5 bit name wkp0 pcr50 pin function setting value 0 0 p50 input pin 1 p50 output pin 1 x wkp0 input pin [legend] x: don't care.
section 9 i/o ports rev. 3.00 sep. 10, 2007 page 151 of 528 rej09b0216-0300 9.5 port 6 port 6 is a general i/o port also functioning as a timer z i/o pin. each pin of the port 6 is shown in figure 9.5. the register setting of the timer z has priority for functions of the pins for both uses. p67/ftiod1 p66/ftioc1 p65/ftiob1 p64/ftioa1 p63/ftiod0 p62/ftioc0 p61/ftiob0 p60/ftioa0 port 6 figure 9.5 port 6 pin configuration port 6 has the following registers. ? port control register 6 (pcr6) ? port data register 6 (pdr6) 9.5.1 port control register 6 (pcr6) pcr6 selects inputs/outputs in bit units for pins to be used as general i/o ports of port 6. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pcr67 pcr66 pcr65 pcr64 pcr63 pcr62 pcr61 pcr60 0 0 0 0 0 0 0 0 w w w w w w w w when each of the port 6 pins p67 to p60 functions as a general i/o port, setting a pcr6 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port.
section 9 i/o ports rev. 3.00 sep. 10, 2007 page 152 of 528 rej09b0216-0300 9.5.2 port data register 6 (pdr6) pdr6 is a general i/o port data register of port 6. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p67 p66 p65 p64 p63 p62 p61 p60 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w stores output data for port 6 pins. if pdr6 is read while pcr6 bits are set to 1, the value stored in pdr6 are read. if pdr6 is read while pcr6 bits are cleared to 0, the pin states are read regardless of the value stored in pdr6. 9.5.3 pin functions the correspondence between the register specification and the port functions is shown below. p67/ftiod1 pin register toer tfcr tpmr tiorc1 pcr6 bit name ed1 cmd1 and cmd0 pwmd1 iod2 to iod0 pcr67 pin function setting value 1 00 0 0 p67 input/ftiod1 input pin 000 or 1xx 1 p67 output pin 0 00 0 001 or 01x x ftiod1 output pin 1 xxx other than 00 x xxx [legend] x: don't care.
section 9 i/o ports rev. 3.00 sep. 10, 2007 page 153 of 528 rej09b0216-0300 p66/ftioc1 pin register toer tfcr tpmr tiorc1 pcr6 bit name ec1 cmd1 and cmd0 pwmc1 ioc2 to ioc0 pcr66 pin function setting value 1 00 0 0 p66 input/ftioc1 input pin 000 or 1xx 1 p66 output pin 0 00 0 001 or 01x x ftioc1 output pin 1 xxx other than 00 x xxx [legend] x: don't care. p65/ftiob1 pin register toer tfcr tpmr tiora1 pcr6 bit name eb1 cmd1 to cmd0 pwmb1 iob2 to iob0 pcr65 pin function setting value 1 00 0 0 p65 input/ftiob1 input pin 000 or 1xx 1 p65 output pin 0 00 0 001 or 01x x ftiob1 output pin 1 xxx other than 00 x xxx [legend] x: don't care.
section 9 i/o ports rev. 3.00 sep. 10, 2007 page 154 of 528 rej09b0216-0300 p64/ftioa1 pin register toer tfcr tiora1 pcr6 bit name eb1 cmd1 to cmd0 ioa2 to ioa0 pcr64 pin function setting value 1 xx 0 p64 input/ftioa1 input pin 000 or 1xx 1 p64 output pin 0 00 001 or 01x x ftioa1 output pin [legend] x: don't care. p63/ftiod0 pin register toer tfcr tpmr tiorc0 pcr6 bit name ed0 cmd1 to cmd0 pwmd0 iod2 to iod0 pcr63 pin function setting value 1 00 0 0 p63 input/ftiod0 input pin 000 or 1xx 1 p63 output pin 0 00 0 001 or 01x x ftiod0 output pin 1 xxx other than 00 x xxx [legend] x: don't care. p62/ftioc0 pin register toer tfcr tpmr tiorc0 pcr6 bit name ec0 cmd1 to cmd0 pwmc0 ioc2 to ioc0 pcr62 pin function setting value 1 00 0 0 p62 input/ftioc0 input pin 000 or 1xx 1 p62 output pin 0 00 0 001 or 01x x ftioc0 output pin 1 xxx other than 00 x xxx [legend] x: don't care.
section 9 i/o ports rev. 3.00 sep. 10, 2007 page 155 of 528 rej09b0216-0300 p61/ftiob0 pin register toer tfcr tpmr tiora0 pcr6 bit name eb0 cmd1 to cmd0 pwmb0 iob2 to iob0 pcr61 pin function setting value 1 00 0 0 p61 input/ftiob0 input pin 000 or 1xx 1 p61 output pin 0 00 0 001 or 01x x ftiob0 output pin 1 xxx other than 00 x xxx [legend] x: don't care. p60/ftioa0 pin register toer tfcr tfcr tiora0 pcr6 bit name ea0 cmd1 to cmd0 stclk ioa2 to ioa0 pcr60 pin function setting value 1 xx x 0 p60 input/ftioa0 input pin 000 or 1xx 1 p60 output pin 0 00 0 001 or 01x x ftioa0 output pin [legend] x: don't care.
section 9 i/o ports rev. 3.00 sep. 10, 2007 page 156 of 528 rej09b0216-0300 9.6 port 7 port 7 is a general i/o port also functioning as a timer v i/o pin and sci3_2 i/o pin. each pin of the port 7 is shown in figure 9.6. the register settings of the timer v and sci3_2 have priority for functions of the pins for both uses. p76/tmov p75/tmciv p74/tmriv p72/txd_2 p71/rxd_2 p70/sck3_2 port 7 figure 9.6 port 7 pin configuration port 7 has the following registers. ? port control register 7 (pcr7) ? port data register 7 (pdr7) 9.6.1 port control register 7 (pcr7) pcr7 selects inputs/outputs in bit units for pins to be used as general i/o ports of port 7. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 ? pcr76 pcr75 pcr74 ? pcr72 pcr71 pcr70 ? 0 0 0 ? 0 0 0 ? w w w ? w w w when each of the port 7 pins p76 to p74 and p72 to p70 functions as a general i/o port, setting a pcr7 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. bits 7 and 3 are reserved bits.
section 9 i/o ports rev. 3.00 sep. 10, 2007 page 157 of 528 rej09b0216-0300 9.6.2 port data register 7 (pdr7) pdr7 is a general i/o port data register of port 7. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 ? p76 p75 p74 ? p72 p71 p70 1 0 0 0 1 0 0 0 ? r/w r/w r/w ? r/w r/w r/w stores output data for port 7 pins. if pdr7 is read while pcr7 bits are set to 1, the value stored in pdr7 are read. if pdr7 is read while pcr7 bits are cleared to 0, the pin states are read regardless of the value stored in pdr7. bits 7 and 3 are reserved bits. these bits are always read as 1. 9.6.3 pin functions the correspondence between the register specification and the port functions is shown below. p76/tmov pin register tcsrv pcr7 bit name os3 to os0 pcr76 pin function setting value 0000 0 p76 input pin 1 p76 output pin other than the above values x tmov output pin [legend] x: don't care. p75/tmciv pin register pcr7 bit name pcr75 pin function setting value 0 p75 input/tmciv input pin 1 p75 output/tmciv input pin
section 9 i/o ports rev. 3.00 sep. 10, 2007 page 158 of 528 rej09b0216-0300 p74/tmriv pin register pcr7 bit name pcr74 pin function setting value 0 p74 input/tmriv input pin 1 p74 output/tmriv input pin p72/txd_2 pin register pmr1 pcr7 bit name txd2 pcr72 pin function setting value 0 0 p72 input pin 1 p72 output pin 1 x txd_2 output pin [legend] x: don't care. p71/rxd_2 pin register scr3_2 pcr7 bit name re pcr71 pin function setting value 0 0 p71 input pin 1 p71 output pin 1 x rxd_2 input pin [legend] x: don't care. p70/sck3_2 pin register scr3_2 smr2 pcr7 bit name cke1 cke0 com pcr70 pin function setting value 0 0 0 0 p70 input pin 1 p70 output pin 0 0 1 x sck3_2 output pin 0 1 x x sck3_2 output pin 1 x x x sck3_2 input pin [legend] x: don't care.
section 9 i/o ports rev. 3.00 sep. 10, 2007 page 159 of 528 rej09b0216-0300 9.7 port 8 port 8 is a general i/o port. each pin of the port 8 is shown in figure 9.7. p87 p86 p85 port 8 figure 9.7 port 8 pin configuration port 8 has the following registers. ? port control register 8 (pcr8) ? port data register 8 (pdr8) 9.7.1 port control register 8 (pcr8) pcr8 selects inputs/outputs in bit units for pins to be used as general i/o ports of port 8. bit bit name initial value r/w description 7 6 5 pcr87 pcr86 pcr85 0 0 0 w w w when each of the port 8 pins p87 to p85 functions as a general i/o port, setting a pcr8 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. 4 to 0 ? ? ? reserved 9.7.2 port data register 8 (pdr8) pdr8 is a general i/o port data register of port 8. bit bit name initial value r/w description 7 6 5 p87 p86 p85 0 0 0 r/w r/w r/w pdr8 stores output data for port 8 pins. if pdr8 is read while pcr8 bits are set to 1, the value stored in pdr8 is read. if pdr8 is read while pcr8 bits are cleared to 0, the pin states are read regardless of the value stored in pdr8. 4 to 0 ? all 1 ? reserved these bits are always read as 1.
section 9 i/o ports rev. 3.00 sep. 10, 2007 page 160 of 528 rej09b0216-0300 9.7.3 pin functions the correspondence between the register specification and the port functions is shown below. p87 pin register pcr8 bit name pcr87 pin function setting value 0 p87 input pin 1 p87 output pin p86 pin register pcr8 bit name pcr86 pin function setting value 0 p86 input pin 1 p86 output pin p85 pin register pcr8 bit name pcr85 pin function setting value 0 p85 input pin 1 p85 output pin
section 9 i/o ports rev. 3.00 sep. 10, 2007 page 161 of 528 rej09b0216-0300 9.8 port b port b is an input port also functioning as an a/d converter analog input pin. each pin of the port b is shown in figure 9.8. pb7/an7/extu pb6/an6/extd pb5/an5 pb4/an4 pb3/an3 pb2/an2 pb1/an1 pb0/an0 port b figure 9.8 port b pin configuration port b has the following register. ? port data register b (pdrb) 9.8.1 port data register b (pdrb) pdrb is a general input-only port data register of port b. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 ? ? ? ? ? ? ? ? r r r r r r r r the input value of each pin is read by reading this register. however, if a port b pin is designated as an analog input channel by adcsr in the a/d converter or as an external comparison voltage input pin by lvdcr in the low- voltage detection circuit, the corresponding bit is read as 0.
section 9 i/o ports rev. 3.00 sep. 10, 2007 page 162 of 528 rej09b0216-0300 9.8.2 pin functions the correspondence between the register specification and the port functions is shown below. pb0/an0 pin register adcsr bit name scan ch2 ch1 ch0 pin function 0 0 0 1 0 x x an0 input pin setting value other than above pb0 output pin [legend] x: don't care. pb1/an1 pin register adcsr bit name scan ch2 ch1 ch0 pin function 0 0 1 0 1 1 0 1 x an1 input pin setting value other than above pb1 output pin [legend] x: don't care. pb2/an2 pin register adcsr bit name scan ch2 ch1 ch0 pin function 0 1 0 1 0 1 x an2 input pin setting value other than above pb2 output pin [legend] x: don't care.
section 9 i/o ports rev. 3.00 sep. 10, 2007 page 163 of 528 rej09b0216-0300 pb3/an3 pin register adcsr bit name scan ch2 ch1 ch0 pin function 0 1 0 1 1 an3 input pin setting value other than above pb3 output pin pb4/an4 pin register adcsr bit name scan ch2 ch1 ch0 pin function 0 0 0 1 1 x x an4 input pin setting value other than above pb4 output pin [legend] x: don't care. pb5/an5 pin register adcsr bit name scan ch2 ch1 ch0 pin function 0 0 1 0 1 1 1 1 x an5 input pin setting value other than above pb5 output pin [legend] x: don't care.
section 9 i/o ports rev. 3.00 sep. 10, 2007 page 164 of 528 rej09b0216-0300 pb6/an6/extd pin register adcsr lvdcr bit name scan ch2 ch1 ch0 vddii pin function 0 0 1 x 0 an6 input/extd input pin 0 0 1 1 x 1 an6 input pin 0 pb6 input/extd input pin setting value other than above 1 pb6 input pin [legend] x: don't care. pb7/an7/extu pin register adcsr lvdcr bit name scan ch2 ch1 ch0 vddii pin function 0 1 0 an7 input/extu input pin 0 1 1 1 an7 input pin 0 pb7 input/extu input pin setting value other than above 1 pb7 input pin [legend] x: don't care.
section 9 i/o ports rev. 3.00 sep. 10, 2007 page 165 of 528 rej09b0216-0300 9.9 port c port c is a general i/o port also functioning as an external oscillation pin and clock output pin. each pin of the port c is shown in figure 9.9. the register setting of ckcsr has priority for functions of the pins for both uses. pc1/osc2/clkout pc0/osc1 port c figure 9.9 port c pin configuration port c has the following registers. ? port control register c (pcrc) port data register c (pdrc) 9.9.1 port control register c (pcrc) pcrc selects inputs/outputs in bit units for pins to be used as general i/o ports of port c. bit bit name initial value r/w description 7 to 2 ? ? ? reserved 1 0 pcrc1 pcrc0 0 0 w w when each of the port c pins, pc1 and pc0, functions as an general i/o port, setting a pcrc bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port.
section 9 i/o ports rev. 3.00 sep. 10, 2007 page 166 of 528 rej09b0216-0300 9.9.2 port data register c (pdrc) pdrc is a general i/o port data register of port c. bit bit name initial value r/w description 7 to 2 ? ? ? reserved 1 0 pc1 pc0 0 0 r/w r/w these bits store output data for port c pins. if pdrc is read while pcrc bits are set to 1, the value stored in pdrc is read. if pdrc is read while pcrc bits are cleared to 0, the pin states are read regardless of the value stored in pdrc. 9.9.3 pin functions the correspondence between the register specification and the port functions is shown below. pc1/osc2/clkout pin register ckcsr pcrc bit name pmrc1 pmrc0 pcrc1 pin function 0 pc1 input pin 0 1 pc1 output pin 0 1 x open 0 x clkout output pin setting value 1 1 x osc2 oscillation pin [legend] x: don't care. pc0/osc1 pin register ckcsr pcrc bit name pmrc0 pcrc0 pin function 0 pc0 input pin 0 1 pc0 output pin setting value 1 x osc1 oscillation pin [legend] x: don't care.
section 10 realtime clock (rtc) rtc3000a_000020030300 rev. 3.00 sep. 10, 2007 page 167 of 528 rej09b0216-0300 section 10 realtime clock (rtc) the realtime clock (rtc) is a timer used to count time ranging from a second to a week. figure 10.1 shows the block diagram of the rtc. 10.1 features ? counts seconds, minutes, hours, and day-of-week ? start/stop function ? reset function ? readable/writable counter of seconds, minutes, hours, and day-of-week with bcd codes ? periodic (seconds, minutes, hours, days, and weeks) interrupts ? 8-bit free running counter ? selection of clock source pss 32-khz oscillator circuit rtccsr rsecdr rmindr rwkdr clock count control circuit interrupt control circuit interrupt rtccr1 rhrdr rtccr2 internal data bus 1/4 tmow [legend] rtccsr: rsecdr: rmindr: rhrdr: rwkdr: rtccr1: rtccr2: pss: clock source select register second date register/free running counter data register minute date register hour date register day-of-week date register rtc control register 1 rtc control register 2 prescaler s figure 10.1 block diagram of rtc
section 10 realtime clock (rtc) rev. 3.00 sep. 10, 2007 page 168 of 528 rej09b0216-0300 10.2 input/output pin table 10.1 shows the rtc input/output pin. table 10.1 pin configuration name abbreviation i/o function clock output tmow output rtc divided clock output
section 10 realtime clock (rtc) rev. 3.00 sep. 10, 2007 page 169 of 528 rej09b0216-0300 10.3 register descriptions the rtc has the following registers. ? second data register/free running counter data register (rsecdr) ? minute data register (rmindr) ? hour data register (rhrdr) ? day-of-week data register (rwkdr) ? rtc control register 1 (rtccr1) ? rtc control register 2 (rtccr2) ? clock source select register (rtccsr) 10.3.1 second data register/free running counter data register (rsecdr) rsecdr counts the bcd-coded second value. the setti ng range is decimal 00 to 59. it is an 8-bit read register used as a counter, when it operates as a free running counter. for more information on reading seconds, minutes, hours, and day-of-week, see section 10.4.3, data reading procedure. bit bit name initial value r/w description 7 bsy ? r rtc busy this bit is set to 1 when the rtc is updating (operating) the values of second, minute, hour, and day-of-week data registers. when this bit is 0, the values of second, minute, hour, and day-of-week data registers must be adopted. 6 5 4 sc12 sc11 sc10 ? ? ? r/w r/w r/w counting ten's position of seconds counts on 0 to 5 for 60-second counting. 3 2 1 0 sc03 sc02 sc01 sc00 ? ? ? ? r/w r/w r/w r/w counting one's position of seconds counts on 0 to 9 once per second. when a carry is generated, 1 is added to the ten's position.
section 10 realtime clock (rtc) rev. 3.00 sep. 10, 2007 page 170 of 528 rej09b0216-0300 10.3.2 minute data register (rmindr) rmindr counts the bcd-coded minute value on the carry generated once per minute by the rsecdr counting. the setting range is decimal 00 to 59. bit bit name initial value r/w description 7 bsy ? r rtc busy this bit is set to 1 when the rtc is updating (operating) the values of second, minute, hour, and day-of-week data registers. when this bit is 0, the values of second, minute, hour, and day-of-week data registers must be adopted. 6 5 4 mn12 mn11 mn10 ? ? ? r/w r/w r/w counting ten's position of minutes counts on 0 to 5 for 60-minute counting. 3 2 1 0 mn03 mn02 mn01 mn00 ? ? ? ? r/w r/w r/w r/w counting one's position of minutes counts on 0 to 9 once per minute. when a carry is generated, 1 is added to the ten's position.
section 10 realtime clock (rtc) rev. 3.00 sep. 10, 2007 page 171 of 528 rej09b0216-0300 10.3.3 hour data register (rhrdr) rhrdr counts the bcd-coded hour value on the carry generated once per hour by rmindr. the setting range is either decimal 00 to 11 or 00 to 23 by the selection of the 12/24 bit in rtccr1. bit bit name initial value r/w description 7 bsy ? r rtc busy this bit is set to 1 when the rtc is updating (operating) the values of second, minute, hour, and day-of-week data registers. when this bit is 0, the values of second, minute, hour, and day-of-week data registers must be adopted. 6 ? 0 ? reserved this bit is always read as 0. 5 4 hr11 hr10 ? ? r/w r/w counting ten's position of hours counts on 0 to 2 for ten's position of hours. 3 2 1 0 hr03 hr02 hr01 hr00 ? ? ? ? r/w r/w r/w r/w counting one's position of hours counts on 0 to 9 once per hour. when a carry is generated, 1 is added to the ten's position.
section 10 realtime clock (rtc) rev. 3.00 sep. 10, 2007 page 172 of 528 rej09b0216-0300 10.3.4 day-of-week data register (rwkdr) rwkdr counts the bcd-coded day-of-week value on the carry generated once per day by rhrdr. the setting range is decimal 0 to 6 using bits wk2 to wk0. bit bit name initial value r/w description 7 bsy ? r rtc busy this bit is set to 1 when the rtc is updating (operating) the values of second, minute, hour, and day-of-week data registers. when this bit is 0, the values of second, minute, hour, and day-of-week data registers must be adopted. 6 to 3 ? all 0 ? reserved these bits are always read as 0. 2 1 0 wk2 wk1 wk0 ? ? ? r/w r/w r/w day-of-week counting day-of-week is indicated with a binary code 000: sunday 001: monday 010: tuesday 011: wednesday 100: thursday 101: friday 110: saturday 111: reserved (setting prohibited)
section 10 realtime clock (rtc) rev. 3.00 sep. 10, 2007 page 173 of 528 rej09b0216-0300 10.3.5 rtc control register 1 (rtccr1) rtccr1 controls start/stop and reset of the clock timer. for the definition of time expression, see figure 10.2. bit bit name initial value r/w description 7 run ? r/w rtc operation start 0: stops rtc operation 1: starts rtc operation 6 12/24 ? r/w operating mode 0: rtc operates in 12- hour mode. rhrdr counts on 0 to 11. 1: rtc operates in 24- hour mode. rhrdr counts on 0 to 23. 5 pm ? r/w a.m./p.m. 0: indicates a.m. when rtc is in the 12-hour mode. 1: indicates p.m. when rtc is in the 12-hour mode. 4 rst 0 r/w reset 0: normal operation 1: resets registers and control circuits except rtccsr and this bit. clear this bit to 0 after having been set to 1. 3 int ? r/w interrupt generation timing 0: generates a second, minute, hour, or day-of-week periodic interrupt during rtc busy period. 1: generates a second, minute, hour, or day-of-week periodic interrupt immediately after completing rtc busy period. 2 to 0 ? all 0 ? reserved these bits are always read as 0. 24-hour count 01234567891011121314151617 12-hour count 0 pm 24-hour count 12-hour count pm 0 (morning) 1 (afternoon) noon 123456789101101234 5 18 19 20 21 22 23 0 6 1 (afternoon) 0 7 8 9 10 11 0 figure 10.2 definition of time expression
section 10 realtime clock (rtc) rev. 3.00 sep. 10, 2007 page 174 of 528 rej09b0216-0300 10.3.6 rtc control register 2 (rtccr2) rtccr2 controls rtc periodic interrupts of weeks, days, hours, minutes, and seconds. enabling interrupts of weeks, days, hours, minutes, and seconds sets the irrta flag to 1 in the interrupt flag register 1 (irr1) when an interrupt occurs. it also controls an overflow interrupt of a free running counter when rtc operates as a free running counter. bit bit name initial value r/w description 7, 6 ? all 0 ? reserved these bits are always read as 0. 5 foie ? r/w free running counter overflow interrupt enable 0: disables an overflow interrupt 1: enables an overflow interrupt 4 wkie ? r/w week periodic interrupt enable 0: disables a week periodic interrupt 1: enables a week periodic interrupt 3 dyie ? r/w day periodic interrupt enable 0: disables a day periodic interrupt 1: enables a day periodic interrupt 2 hrie ? r/w hour periodic interrupt enable 0: disables an hour periodic interrupt 1: enables an hour periodic interrupt 1 mnie ? r/w minute periodic interrupt enable 0: disables a minute periodic interrupt 1: enables a minute periodic interrupt 0 seie ? r/w second periodic interrupt enable 0: disables a second periodic interrupt 1: enables a second periodic interrupt
section 10 realtime clock (rtc) rev. 3.00 sep. 10, 2007 page 175 of 528 rej09b0216-0300 10.3.7 clock source select register (rtccsr) rtccsr selects clock source. a free running counte r controls start/stop of counter operation by the run bit in rtccr1. when a clock other than 32.768 khz is selected, the rtc is disabled and operates as an 8-bit free running counter. when the rtc operates as an 8-bit free running counter, rsecdr enables counter values to be re ad. an interrupt can be generated by setting 1 to the foie bit in rtccr2 and enabling an overflow interrupt of the free running counter. a clock in which the system clock is divided by 32, 16, 8, or 4 is output in active or sleep mode. bit bit name initial value r/w description 7 ? 0 ? reserved this bit is always read as 0. 6 5 rcs6 rcs5 0 0 r/w r/w clock output selection selects a clock output from the tmow pin when setting tmow in pmr1 to 1. 00: /4 01: /8 10: /16 11: /32 4 ? 0 ? reserved this bit is always read as 0. 3 2 1 0 rcs3 rcs2 rcs1 rcs0 1 0 0 0 r/w r/w r/w r/w clock source selection 0000: /8 ?????????????????? free running counter operation 0001: /32 ???????????????? free running counter operation 0010: /128 ?????????????? free running counter operation 0011: /256 ?????????????? free running counter operation 0100: /512 ?????????????? free running counter operation 0101: /2048 ???????????? free running counter operation 0110: /4096 ???????????? free running counter operation 0111: /8192 ???????????? free running counter operation 1xxx: 32.768 khz ??? rtc operation [legend] x: don't care.
section 10 realtime clock (rtc) rev. 3.00 sep. 10, 2007 page 176 of 528 rej09b0216-0300 10.4 operation 10.4.1 initial settings of registers after power-on the rtc registers that store second, minute, hour, and day-of week data are not reset by a res input. therefore, all registers must be set to thei r initial values after power-on. once the register setting are made, the rtc provides an accurate time as long as power is supplied regardless of a res input. 10.4.2 initial setting procedure figure 10.3 shows the procedure for the initial setting of the rtc. to set the rtc again, also follow this procedure. rtc operation is stopped. rtc registers and clock count controller are reset. clock output and clock source are selected and second, minute, hour, day-of-week,operating mode, and a.m/p.m are set. rtc operation is started. run in rtccr1=0 rst in rtccr1=1 rst in rtccr1=0 set rtccsr, rsecdr, rmindr,rhrdr, rwkdr,12/24 in rtccr1, and pm run in rtccr1=1 figure 10.3 initial setting procedure
section 10 realtime clock (rtc) rev. 3.00 sep. 10, 2007 page 177 of 528 rej09b0216-0300 10.4.3 data reading procedure when the seconds, minutes, hours, or day-of-week datum is updated while time data is being read, the data obtained may not be correct, and so the time data must be read again. figure 10.4 shows an example in which correct data is not obtained. in this example, since only rsecdr is read after data update, about 1-minute inconsistency occurs. to avoid reading in this timing, the following processing must be performed. 1. check the setting of the bsy bit, and when the bsy bit changes from 1 to 0, read from the second, minute, hour, and day-of-week registers. when about 62.5 ms is passed after the bsy bit is set to 1, the registers are updated, and the bsy bit is cleared to 0. 2. making use of interrupts, read from the second, minute, hour, and day-of week registers after the irrta flag in irr1 is set to 1 and the bsy bit is confirmed to be 0. 3. read from the second, minute, hour, and day-of week registers twice in a row, and if there is no change in the read data, the read data is used. before update rwkdr = h'03, rhddr = h'13, rmindr = h'46, rsecdr = h'59 bsy bit = 0 (1) day-of-week data register read h'03 (2) hour data register read h'13 (3) minute data register read h'46 bsy bit -> 1 (under data update) after update rwkdr = h'03, rhddr = h'13, rmindr = h'47, rsecdr = h'00 bsy bit -> 0 (4) second data register read h'00 processing flow figure 10.4 example: reading of inaccurate time data
section 10 realtime clock (rtc) rev. 3.00 sep. 10, 2007 page 178 of 528 rej09b0216-0300 10.5 interrupt sources there are five kinds of rtc interrupts: week interrupts, day interrupts, hour interrupts, minute interrupts, and second interrupts. when using an interrupt, initiate the rtc last after other registers are set. do not set multiple interrupt enable bits in rtccr2 simultaneously to 1. when an interrupt request of the rtc occurs, the irrta flag in irr1 is set to 1. when clearing the flag, write 0. table 10.2 interrupt sources interrupt name interrupt source interrupt enable bit overflow interrupt occurs when the free running counter is overflowed. foie week periodic interrupt occurs every week when the day-of-week date register value becomes 0. wkie day periodic interrupt occurs every day when the day-of-week date register is counted. dyie hour periodic interrupt occurs every hour when the hour date register is counted. hrie minute periodic interrupt occurs every minute when the minute date register is counted. mnie second periodic interrupt occurs every second when the second date register is counted. scie
section 11 timer b1 tim08b0a_000020020200 rev. 3.00 sep. 10, 2007 page 179 of 528 rej09b0216-0300 section 11 timer b1 timer b1 is an 8-bit timer that increments each time a clock pulse is input. this timer has two operating modes, interval and auto reload. figure 11.1 shows a block diagram of timer b1. 11.1 features ? selection of seven internal clock sources ( /8192, /2048, /512, /256, /64, /16, and /4) or an external clock (can be used to count external events). ? an interrupt is generated when the counter overflows. [legend] tmb1: tmib1 tcb1: timer mode register b1 timer counter b1 tlb1: irrtb1: timer load register b1 timer b1 interrupt request flag pss: tmib1: prescaler s timer b1 event input internal data bus tcb1 tmb1 pss tlb1 irrtb1 figure 11.1 block diagram of timer b1
section 11 timer b1 rev. 3.00 sep. 10, 2007 page 180 of 528 rej09b0216-0300 11.2 input/output pin table 11.1 shows the timer b1 pin configuration. table 11.1 pin configuration name abbreviation i/o function timer b1 event input tmib1 input event input to tcb1
section 11 timer b1 rev. 3.00 sep. 10, 2007 page 181 of 528 rej09b0216-0300 11.3 register descriptions the timer b1 has the following registers. ? timer mode register b1 (tmb1) ? timer counter b1 (tcb1) ? timer load register b1 (tlb1) 11.3.1 timer mode register b1 (tmb1) tmb1 selects the auto-reload function and input clock. bit bit name initial value r/w description 7 tmb17 0 r/w auto-reload function select 0: interval timer function selected 1: auto-reload function selected 6 to 3 ? all 1 ? reserved these bits are always read as 1. 2 1 0 tmb12 tmb11 tmb10 0 0 0 r/w r/w r/w clock select 000: internal clock: /8192 001: internal clock: /2048 010: internal clock: /512 011: internal clock: /256 100: internal clock: /64 101: internal clock: /16 110: internal clock: /4 111: external event (tmib1): rising or falling edge * note: * the edge of the external event signal is selected by bit ieg1 in the interrupt edge select register 1 (iegr1). see section 3.2.1, interrupt edge select register 1 (iegr1), for details. before setting tmb12 to tmb10 to 1, irq1 in the port mode register 1 (pmr1) should be set to 1.
section 11 timer b1 rev. 3.00 sep. 10, 2007 page 182 of 528 rej09b0216-0300 11.3.2 timer counter b1 (tcb1) tcb1 is an 8-bit read-only up-counter, which is incremented by internal clock input. the clock source for input to this counter is selected by bits tmb12 to tmb10 in tmb1. tcb1 values can be read by the cpu at any time. when tcb1 overflows from h'ff to h'00 or to the value set in tlb1, the irrtb1 flag in irr2 is set to 1. tcb1 is allocated to the same address as tlb1. tcb1 is initialized to h'00. 11.3.3 timer load register b1 (tlb1) tlb1 is an 8-bit write-only register for setting the reload value of tcb1. when a reload value is set in tlb1, the same value is loaded into tcb1 as well, and tcb1 starts counting up from that value. when tcb1 overflows during operation in auto-reload mode, the tlb1 value is loaded into tcb1. accordingly, overflow periods can be set within the range of 1 to 256 input clocks. tlb1 is allocated to the same address as tcb1. tlb1 is initialized to h'00. 11.4 operation 11.4.1 interval timer operation when bit tmb17 in tmb1 is cleared to 0, timer b1 functions as an 8-bit interval timer. upon reset, tcb1 is cleared to h'00 and bit tmb17 is cleared to 0, so up-counting and interval timing resume immediately. the operating clock of timer b1 is selected from seven internal clock signals output by prescaler s, or an external clock input at pin tmb1. the selection is made by bits tmb12 to tmb10 in tmb1. after the count value in tmb1 reaches h'ff, the next clock signal input causes timer b1 to overflow, setting flag irrtb1 in irr2 to 1. if ientb1 in ienr2 is 1, an interrupt is requested to the cpu. at overflow, tcb1 returns to h'00 and starts counting up again. during interval timer operation (tmb17 = 0), when a value is set in tlb1, the same value is set in tcb1.
section 11 timer b1 rev. 3.00 sep. 10, 2007 page 183 of 528 rej09b0216-0300 11.4.2 auto-reload timer operation setting bit tmb17 in tmb1 to 1 causes timer b1 to function as an 8-bit auto-reload timer. when a reload value is set in tlb1, the same value is loaded into tcb1, becoming the value from which tcb1 starts its count. after the count value in tcb1 reaches h'ff, the next clock signal input causes timer b1 to overflow. the tlb1 value is then loaded into tcb1, and the count continues from that value. the overflow period can be set within a range from 1 to 256 input clocks, depending on the tlb1 value. the clock sources and interrupts in auto-reload mode are the same as in interval mode. in auto- reload mode (tmb17 = 1), when a new value is se t in tlb1, the tlb1 value is also loaded into tcb1. 11.4.3 event counter operation timer b1 can operate as an event counter in which tmib1 is set to an event input pin. external event counting is selected by setting bits tmb12 to tmb10 in tmb1 to 1. tcb1 counts up at rising or falling edge of an external event signal input at pin tmb1. when timer b1 is used to count external event input, bit irq1 in pmr1 should be set to 1 and ien1 in ienr1 should be cleared to 0 to disable irq1 interrupt requests. 11.5 timer b1 operating modes table 11.2 shows the timer b1 operating modes. table 11.2 timer b1 operating modes operating mode reset active sleep subactive subsleep standby interval reset functions functions halted halted halted tcb1 auto-reload reset functions functions halted halted halted tmb1 reset functions retained retained retained retained
section 11 timer b1 rev. 3.00 sep. 10, 2007 page 184 of 528 rej09b0216-0300
section 12 timer v tim08v0a_000120030300 rev. 3.00 sep. 10, 2007 page 185 of 528 rej09b0216-0300 section 12 timer v timer v is an 8-bit timer based on an 8-bit counter. timer v counts external events. compare- match signals with two registers can also be used to reset the counter, request an interrupt, or output a pulse signal with an arbitrary duty cycle. counting can be initiated by a trigger input at the trgv pin, enabling pulse output control to be synchronized to the trigger, with an arbitrary delay from the trigger input. figure 12.1 shows a block diagram of timer v. 12.1 features ? choice of seven clock signals is available. choice of six internal clock sources ( /128, /64, /32, /16, /8, /4) or an external clock. ? counter can be cleared by compare match a or b, or by an external reset signal. if the count stop function is selected, the counter can be halted when cleared. ? timer output is controlled by two independent compare match signals, enabling pulse output with an arbitrary duty cycle, pwm output, and other applications. ? three interrupt sources: compare match a, compare match b, timer overflow ? counting can be initiated by trigger input at the trgv pin. the rising edge, falling edge, or both edges of the trgv input can be selected.
section 12 timer v rev. 3.00 sep. 10, 2007 page 186 of 528 rej09b0216-0300 trgv tmciv tmriv tmov trigger control clock select clear control output control pss tcrv1 tcorb comparator tcntv comparator tcora tcrv0 interrupt request control tcsrv cmia cmib ovi internal data bus [legend] tcora: time constant register a tcorb: time constant register b tcntv: timer counter v tcsrv: timer control/status register v tcrv0: timer control register v0 tcrv1: timer control register v1 pss: prescaler s cmia: compare-match interrupt a cmib: compare-match interrupt b ovi: overflow interupt figure 12.1 block diagram of timer v
section 12 timer v rev. 3.00 sep. 10, 2007 page 187 of 528 rej09b0216-0300 12.2 input/output pins table 12.1 shows the timer v pin configuration. table 12.1 pin configuration name abbreviation i/o function timer v output tmov output timer v waveform output timer v clock input tmciv input clock input to tcntv timer v reset input tmriv input external input to reset tcntv trigger input trgv input trigger input to initiate counting 12.3 register descriptions time v has the following registers. ? timer counter v (tcntv) ? timer constant register a (tcora) ? timer constant register b (tcorb) ? timer control register v0 (tcrv0) ? timer control/status register v (tcsrv) ? timer control register v1 (tcrv1) 12.3.1 timer counter v (tcntv) tcntv is an 8-bit up-counter. the clock source is selected by bits cks2 to cks0 in timer control register v0 (tcrv0). the tcntv value can be read and written by the cpu at any time. tcntv can be cleared by an external reset input signal, or by compare match a or b. the clearing signal is selected by bits cclr1 and cclr0 in tcrv0. when tcntv overflows, ovf is set to 1 in timer control/status register v (tcsrv). tcntv is initialized to h'00.
section 12 timer v rev. 3.00 sep. 10, 2007 page 188 of 528 rej09b0216-0300 12.3.2 time constant registers a and b (tcora, tcorb) tcora and tcorb have the same function. tcora and tcorb are 8-bit read/write registers. tcora and tcntv are compared at all times. when the tcora and tcntv contents match, cmfa is set to 1 in tcsrv. if cmiea is also set to 1 in tcrv0, a cpu interrupt is requested. note that they must not be compared dur ing the t3 state of a tcora write cycle. timer output from the tmov pin can be controlled by the identifying signal (compare match a) and the settings of bits os3 to os0 in tcsrv. tcora and tcorb are initialized to h'ff. 12.3.3 timer control register v0 (tcrv0) tcrv0 selects the input clock signals of tcntv, specifies the clearing conditions of tcntv, and controls each interrupt request. bit bit name initial value r/w description 7 cmieb 0 r/w compare match interrupt enable b when this bit is set to 1, interrupt request from the cmfb bit in tcsrv is enabled. 6 cmiea 0 r/w compare match interrupt enable a when this bit is set to 1, interrupt request from the cmfa bit in tcsrv is enabled. 5 ovie 0 r/w timer overflow interrupt enable when this bit is set to 1, interrupt request from the ovf bit in tcsrv is enabled. 4 3 cclr1 cclr0 0 0 r/w r/w counter clear 1 and 0 these bits specify the clearing conditions of tcntv. 00: clearing is disabled 01: cleared by compare match a 10: cleared by compare match b 11: cleared on the rising edge of the tmriv pin. the operation of tcntv after clearing depends on trge in tcrv1.
section 12 timer v rev. 3.00 sep. 10, 2007 page 189 of 528 rej09b0216-0300 bit bit name initial value r/w description 2 1 0 cks2 cks1 cks0 0 0 0 r/w r/w r/w clock select 2 to 0 these bits select clock signals to input to tcntv and the counting condition in combination with icks0 in tcrv1. refer to table 12.2. table 12.2 clock signals to input to tcntv and counting conditions tcrv0 tcrv1 bit 2 bit 1 bit 0 bit 0 cks2 cks1 cks0 icks0 description 0 0 0 ? clock input prohibited 1 0 internal clock: counts on /4, falling edge 1 internal clock: counts on /8, falling edge 1 0 0 internal clock: counts on /16, falling edge 1 internal clock: counts on /32, falling edge 1 0 internal clock: counts on /64, falling edge 1 internal clock: counts on /128, falling edge 1 0 0 ? clock input prohibited 1 ? external clock: counts on rising edge 1 0 ? external clock: counts on falling edge 1 ? external clock: counts on rising and falling edge 12.3.4 timer control/status register v (tcsrv) tcsrv indicates the status flag and controls outputs by using a compare match. bit bit name initial value r/w description 7 cmfb 0 r/w compare match flag b setting condition: when the tcntv value matches the tcorb value clearing condition: after reading cmfb = 1, cleared by writing 0 to cmfb
section 12 timer v rev. 3.00 sep. 10, 2007 page 190 of 528 rej09b0216-0300 bit bit name initial value r/w description 6 cmfa 0 r/w compare match flag a setting condition: when the tcntv value matches the tcora value clearing condition: after reading cmfa = 1, cleared by writing 0 to cmfa 5 ovf 0 r/w timer overflow flag setting condition: when tcntv overflows from h'ff to h'00 clearing condition: after reading ovf = 1, cleared by writing 0 to ovf 4 ? 1 ? reserved this bit is always read as 1. 3 2 os3 os2 0 0 r/w r/w output select 3 and 2 these bits select an output method for the tmov pin by the compare match of tcorb and tcntv. 00: no change 01: 0 output 10: 1 output 11: output toggles 1 0 os1 os0 0 0 r/w r/w output select 1 and 0 these bits select an output method for the tmov pin by the compare match of tcora and tcntv. 00: no change 01: 0 output 10: 1 output 11: output toggles os3 and os2 select the output level for compare match b. os1 and os0 select the output level for compare match a. the two output levels can be controlled independently. after a reset, the timer output is 0 until the first compare match.
section 12 timer v rev. 3.00 sep. 10, 2007 page 191 of 528 rej09b0216-0300 12.3.5 timer control register v1 (tcrv1) tcrv1 selects the edge at the trgv pin, enables trgv input, and selects the clock input to tcntv. bit bit name initial value r/w description 7 to 5 ? all 1 ? reserved these bits are always read as 1. 4 3 tveg1 tveg0 0 0 r/w r/w trgv input edge select these bits select the trgv input edge. 00: trgv trigger input is prohibited 01: rising edge is selected 10: falling edge is selected 11: rising and falling edges are both selected 2 trge 0 r/w tcnt starts counting up by the input of the edge which is selected by tveg1 and tveg0. 0: disables starting counting-up tcntv by the input of the trgv pin and halting counting-up tcntv when tcntv is cleared by a compare match. 1: enables starting counting-up tcntv by the input of the trgv pin and halting counting-up tcntv when tcntv is cleared by a compare match. 1 ? 1 ? reserved this bit is always read as 1. 0 icks0 0 r/w internal clock select 0 this bit selects clock signals to input to tcntv in combination with cks2 to cks0 in tcrv0. refer to table 12.2.
section 12 timer v rev. 3.00 sep. 10, 2007 page 192 of 528 rej09b0216-0300 12.4 operation 12.4.1 timer v operation 1. according to table 12.2, six internal/external clock signals output by prescaler s can be selected as the timer v operating clock signals. when the operating clock signal is selected, tcntv starts counting-up. figure 12.2 shows the count timing with an internal clock signal selected, and figure 12.3 shows the count timing with both edges of an external clock signal selected. 2. when tcntv overflows (changes from h'ff to h'00), the overflow flag (ovf) in tcrv0 will be set. the timing at this time is shown in fi gure 12.4. an interrupt request is sent to the cpu when ovie in tcrv0 is 1. 3. tcntv is constantly compared with tc ora and tcorb. compare match flag a or b (cmfa or cmfb) is set to 1 when tcntv matches tcora or tcorb, respectively. the compare-match signal is generated in the last state in which the values match. figure 12.5 shows the timing. an interrupt request is generated for the cpu when cmiea or cmieb in tcrv0 is 1. 4. when a compare match a or b is generated, the tmov responds with the output value selected by bits os3 to os0 in tcsrv. figure 12.6 shows the timing when the output is toggled by compare match a. 5. when cclr1 or cclr0 in tcrv0 is 01 or 10, tcntv can be cleared by the corresponding compare match. figure 12.7 shows the timing. 6. when cclr1 or cclr0 in tcrv0 is 11, tcntv can be cleared by the rising edge of the input of tmriv pin. a tmriv i nput pulse-width of at least 1. 5 system clocks is necessary. figure 12.8 shows the timing. 7. when a counter-clearing source is generated with trge in tcrv1 set to 1, the counting-up is halted as soon as tcntv is cleared. tcntv resumes counting-up when the edge selected by tveg1 or tveg0 in tcrv1 is input from the tgrv pin.
section 12 timer v rev. 3.00 sep. 10, 2007 page 193 of 528 rej09b0216-0300 n ? 1 n + 1 n internal clock tcntv input clock tcntv figure 12.2 increment timi ng with internal clock n ? 1 n + 1 n tmciv (external clock input pin) tcntv input clock tcntv figure 12.3 increment timi ng with external clock h'ff h'00 tcntv overflow signal ovf figure 12.4 ovf set timing
section 12 timer v rev. 3.00 sep. 10, 2007 page 194 of 528 rej09b0216-0300 n n n+1 tcntv tcora or tcorb compare match signal cmfa or cmfb figure 12.5 cmfa and cmfb set timing compare match a signal timer v output pin figure 12.6 tmov output timing n h'00 compare match a signal tcntv figure 12.7 clear timing by compare match
section 12 timer v rev. 3.00 sep. 10, 2007 page 195 of 528 rej09b0216-0300 tmriv (external counter reset input pin) tcntv reset signal tcntv n ? 1 n h'00 figure 12.8 clear timing by tmriv input 12.5 timer v application examples 12.5.1 pulse output with arbitrary duty cycle figure 12.9 shows an example of output of pulses with an arbitrary duty cycle. 1. set bits cclr1 and cclr0 in tcrv0 so that tcntv will be cleared by compare match with tcora. 2. set bits os3 to os0 in tcsrv so that the output will go to 1 at compare match with tcora and to 0 at compare match with tcorb. 3. set bits cks2 to cks0 in tcrv0 and bit icks0 in tcrv1 to select the desired clock source. 4. with these settings, a waveform is output without further software intervention, with a period determined by tcora and a pulse width determined by tcorb. counter cleared time tcntv value h'ff tcora tcorb h'00 tmov figure 12.9 pulse output example
section 12 timer v rev. 3.00 sep. 10, 2007 page 196 of 528 rej09b0216-0300 12.5.2 pulse output with arbitrary pulse width and delay from trgv input the trigger function can be used to output a pulse with an arbitrary pulse width at an arbitrary delay from the trgv input, as shown in figure 12.10. to set up this output: 1. set bits cclr1 and cclr0 in tcrv0 so that tcntv will be cleared by compare match with tcorb. 2. set bits os3 to os0 in tcsrv so that the output will go to 1 at compare match with tcora and to 0 at compare match with tcorb. 3. set bits tveg1 and tveg0 in tcrv1 and set trge to select the falling edge of the trgv input. 4. set bits cks2 to cks0 in tcrv0 and bit icks0 in tcrv1 to select the desired clock source. 5. after these settings, a pulse waveform will be output without further software intervention, with a delay determined by tcora from the trgv input, and a pulse width determined by (tcorb ? tcora). counter cleared h'ff tcora tcorb h'00 trgv tmov compare match a compare match b clears tcntv and halts count-up compare match b clears tcntv and halts count-up compare match a tcntv value time figure 12.10 example of pulse output synchronized to trgv input
section 12 timer v rev. 3.00 sep. 10, 2007 page 197 of 528 rej09b0216-0300 12.6 usage notes the following types of contention or operation can occur in timer v operation. 1. writing to registers is performed in the t3 state of a tcntv write cycle. if a tcntv clear signal is generated in the t3 state of a tcntv write cycle, as shown in figure 12.11, clearing takes precedence and the write to th e counter is not carried out. if counting-up is generated in the t3 state of a tcntv write cycle, writing takes precedence. 2. if a compare match is generated in the t3 st ate of a tcora or tcorb write cycle, the write to tcora or tcorb takes precedence and the compare match signal is inhibited. figure 12.12 shows the timing. 3. if compare matches a and b occur simultaneously, any conflict between the output selections for compare match a and compare match b is resolved by the following priority: toggle output > output 1 > output 0. 4. depending on the timing, tcntv may be incremented by a switch between different internal clock sources. when tcntv is internally clocked, an increment pulse is generated from the falling edge of an internal clock signal, that is divided system clock ( ). therefore, as shown in figure 12.3 the switch is from a high clock signal to a low clock signal, the switchover is seen as a falling edge, causing tcntv to increment. tcntv can also be incremented by a switch between internal and external clocks. address tcntv address tcntv write cycle by cpu internal write signal counter clear signal tcntv n h'00 t 1 t 2 t 3 figure 12.11 contention between tcntv write and clear
section 12 timer v rev. 3.00 sep. 10, 2007 page 198 of 528 rej09b0216-0300 address tcora address internal write signal tcntv tcora n n n+1 m tcora write data inhibited t 1 t 2 t 3 tcora write cycle by cpu compare match signal figure 12.12 contention between tcora write and compare match clock before switching clock after switching count clock tcntv n n+1 n+2 write to cks1 and cks0 figure 12.13 internal clock switching and tcntv operation
section 13 timer z tim08z0a_000120030300 rev. 3.00 sep. 10, 2007 page 199 of 528 rej09b0216-0300 section 13 timer z the timer z has a 16-bit timer with two channels. figures 13.1, 13.2, and 13.3 show the block diagrams of entire timer z, its channel 0, and its channel 1, respectively. for details on the timer z functions, refer to table 13.1. 13.1 features ? capability to process up to eight inputs/outputs ? eight general registers (gr): f our registers for each channel ? independently assignable output compare or input capture functions ? selection of five counter clock sources: four internal clocks ( , /2, /4, and /8) and an external clock ? seven selectable operating modes ? output compare function selection of 0 output, 1 output, or toggle output ? input capture function rising edge, falling edge, or both edges ? synchronous operation timer counters_0 and _1 (tcnt_0 and tcnt_1) can be written simultaneously. simultaneous clearing by compare match or input capture is possible. ? pwm mode up to six-phase pwm output can be provided with desired duty ratio. ? reset synchronous pwm mode three-phase pwm output for normal and counter phases ? complementary pwm mode three-phase pwm output for non-overlapped normal and counter phases the a/d conversion start trigger can be set for pwm cycles. ? buffer operation the input capture register can be consisted of double buffers. the output compare register can automatically be modified. ? high-speed access by the internal 16-bit bus ? 16-bit tcnt and gr registers can be accessed in high speed by a 16-bit bus interface ? any initial timer output value can be set ? output of the timer is disabled by external trigger
section 13 timer z rev. 3.00 sep. 10, 2007 page 200 of 528 rej09b0216-0300 ? eleven interrupt sources ? four compare match/input capture interrupts and an overflow interrupt are available for each channel. an underflow interrupt can be set for channel 1. table 13.1 timer z functions item channel 0 channel 1 count clock internal clocks: , /2, /4, /8 external clock: ftioa0 (tclk) general registers (output compare/input capture registers) gra_0, grb_0, grc_0, grd_0 gra_1, grb_1, grc_1, grd_1 buffer register grc_0, grd_0 grc_1, grd_1 i/o pins ftioa0, ftiob0, ftioc0, ftiod0 ftioa1, ftiob1, ftioc1, ftiod1 counter clearing function compare match/input capture of gra_0, grb_0, grc_0, or grd_0 compare match/input capture of gra_1, grb_1, grc_1, or grd_1 0 output yes yes 1 output yes yes compare match output output yes yes input capture function yes yes synchronous operation yes yes pwm mode yes yes reset synchronous pwm mode yes yes complementary pwm mode yes yes buffer function yes yes interrupt sources compare match/input capture a0 to d0 overflow compare match/input capture a1 to d1 overflow underflow
section 13 timer z rev. 3.00 sep. 10, 2007 page 201 of 528 rej09b0216-0300 itmz0 ftioa0 itmz1 adtrg channel 0 timer channel 1 timer module data bus ftiob0 ftioc0 ftiod0 ftioa1 ftiob1 ftioc1 ftiod1 tstr: [legend] tmdr: tfcr: toer: tocr: adtrg : itmz0: itmz1: timer start register (8 bits) timer mode register (8 bits) tpmr: timer pwm mode register (8 bits) timer function control register (8 bits) timer output master enable register (8 bits) timer output control register (8 bits) a/d conversion start trigger output signal channel 0 interrupt channel 1 interrupt toer tocr tpmr tfcr tstr tmdr control logic , /2, /4, /8 figure 13.1 timer z block diagram
section 13 timer z rev. 3.00 sep. 10, 2007 page 202 of 528 rej09b0216-0300 itmz0 ftiod0 ftioc0 ftiob0 ftioa0 tcnt_0 gra_0 grb_0 grc_0 grd_0 tcr_0 tiora_0 tsr_0 tiorc_0 tier_0 pocr_0 tcnt_0: gra_0, grb_0, grc_0, grd_0: tcr_0: tiora_0: tier_0: tsr_0: itmz0: timer counter_0 (16 bits) general registers a_0, b_0, c_0, and d_0 (input capture/output compare registers: 16 bits 4) timer control register_0 (8 bits) timer i/o control register a_0 (8 bits) tiorc_0: timer i/o control register c_0 (8 bits) timer interrupt enable register_0 (8 bits) pocr_0: pwm mode output level control register_0 (8 bits) timer status register_0 (8 bits) channel 0 interrupt [legend] , /2, /4, /8 clock select control logic module data bus comparator figure 13.2 timer z (channel 0) block diagram
section 13 timer z rev. 3.00 sep. 10, 2007 page 203 of 528 rej09b0216-0300 itmz1 ftiod1 ftioc1 ftiob1 ftioa1 tcnt_1 gra_1 grb_1 grc_1 grd_1 tcr_1 tiora_1 tsr_1 tiorc_1 tier_1 pocr_1 tcnt_1: gra_1, grb_1, grc_1, grd_1: tcr_1: tiora_1: tier_1: tsr_1: itmz1: timer counter_1 (16 bits) general registers a_1, b_1, c_1, and d_1 (input capture/output compare registers: 16 bits 4) timer control register_1 (8 bits) timer i/o control register a_1 (8 bits) tiorc_1: timer i/o control register c_1 (8 bits) timer interrupt enable register_1 (8 bits) pocr_1: pwm mode output level control register_1 (8 bits) timer status register_1 (8 bits) channel 1 interrupt [legend] , /2, /4, /8 clock select control logic module data bus comparator figure 13.3 timer z (channel 1) block diagram
section 13 timer z rev. 3.00 sep. 10, 2007 page 204 of 528 rej09b0216-0300 13.2 input/output pins table 13.2 summarizes the timer z pins. table 13.2 pin configuration name abbreviation input/output function input capture/output compare a0 ftioa0 input/output gra_0 output compare output, gra_0 input capture input, or external clock input (tclk) input capture/output compare b0 ftiob0 input/output grb_0 output compare output, grb_0 input capture input, or pwm output input capture/output compare c0 ftioc0 input/output grc_0 output compare output, grc_0 input capture input, or pwm synchronous output (in reset synchronous pwm and complementary pwm modes) input capture/output compare d0 ftiod0 input/output grd_0 output compare output, grd_0 input capture input, or pwm output input capture/output compare a1 ftioa1 input/output gra_1 output compare output, gra_1 input capture input, or pwm output (in reset synchronous pwm and complementary pwm modes) input capture/output compare b1 ftiob1 input/output grb_1 output compare output, grb_1 input capture input, or pwm output input capture/output compare c1 ftioc1 input/output grc_1 output compare output, grc_1 input capture input, or pwm output input capture/output compare d1 ftiod1 input/output grd_1 output compare output, grd_1 input capture input, or pwm output
section 13 timer z rev. 3.00 sep. 10, 2007 page 205 of 528 rej09b0216-0300 13.3 register descriptions the timer z has the following registers. common ? timer start register (tstr) ? timer mode register (tmdr) ? timer pwm mode register (tpmr) ? timer function control register (tfcr) ? timer output master enable register (toer) ? timer output control register (tocr) channel 0 ? timer control register_0 (tcr_0) ? timer i/o control register a_0 (tiora_0) ? timer i/o control register c_0 (tiorc_0) ? timer status register_0 (tsr_0) ? timer interrupt enable register_0 (tier_0) ? pwm mode output level control register_0 (pocr_0) ? timer counter_0 (tcnt_0) ? general register a_0 (gra_0) ? general register b_0 (grb_0) ? general register c_0 (grc_0) ? general register d_0 (grd_0) channel 1 ? timer control register_1 (tcr_1) ? timer i/o control register a_1 (tiora_1) ? timer i/o control register c_1 (tiorc_1) ? timer status register_1 (tsr_1) ? timer interrupt enable register_1 (tier_1) ? pwm mode output level control register_1 (pocr_1) ? timer counter_1 (tcnt_1) ? general register a_1 (gra_1) ? general register b_1 (grb_1)
section 13 timer z rev. 3.00 sep. 10, 2007 page 206 of 528 rej09b0216-0300 ? general register c_1 (grc_1) ? general register d_1 (grd_1) 13.3.1 timer start register (tstr) tstr selects the operation/stop for the tcnt counter. bit bit name initial value r/w description 7 to 2 ? all 1 ? reserved these bits are always read as 1, and cannot be modified. 1 str1 0 r/w channel 1 counter start 0: tcnt_1 halts counting 1: tcnt_1 starts counting 0 str0 0 r/w channel 0 counter start 0: tcnt_0 halts counting 1: tcnt_0 starts counting 13.3.2 timer mode register (tmdr) tmdr selects buffer operation settings and synchronized operation. bit bit name initial value r/w description 7 bfd1 0 r/w buffer operation d1 0: grd_1 operates normally 1: grb_1 and grd_1 are used together for buffer operation 6 bfc1 0 r/w buffer operation c1 0: grc_1 operates normally 1: gra_1 and grd_1 are used together for buffer operation 5 bfd0 0 r/w buffer operation d0 0: grd_0 operates normally 1: grb_0 and grd_0 are used together for buffer operation
section 13 timer z rev. 3.00 sep. 10, 2007 page 207 of 528 rej09b0216-0300 bit bit name initial value r/w description 4 bfc0 0 r/w buffer operation c0 0: grc_0 operates normally 1: gra_0 and grc_0 are used together for buffer operation 3 to 1 ? all 1 ? reserved these bits are always read as 1, and cannot be modified. 0 sync 0 r/w timer synchronization 0: tcnt_1 and tcnt_0 operate as a different timer counter 1: tcnt_1 and tcnt_0 are synchronized tcnt_1 and tcnt_0 can be pre-set or cleared synchronously 13.3.3 timer pwm mode register (tpmr) tpmr sets the pin to enter pwm mode. bit bit name initial value r/w description 7 ? 1 ? reserved this bit is always read as 1, and cannot be modified. 6 pwmd1 0 r/w pwm mode d1 0: ftiod1 operates normally 1: ftiod1 operates in pwm mode 5 pwmc1 0 r/w pwm mode c1 0: ftioc1 operates normally 1: ftioc1 operates in pwm mode 4 pwmb1 0 r/w pwm mode b1 0: ftiob1 operates normally 1: ftiob1 operates in pwm mode 3 ? 1 ? reserved this bit is always read as 1, and cannot be modified.
section 13 timer z rev. 3.00 sep. 10, 2007 page 208 of 528 rej09b0216-0300 bit bit name initial value r/w description 2 pwmd0 0 r/w pwm mode d0 0: ftiod0 operates normally 1: ftiod0 operates in pwm mode 1 pwmc0 0 r/w pwm mode c0 0: ftioc0 operates normally 1: ftioc0 operates in pwm mode 0 pwmb0 0 r/w pwm mode b0 0: ftiob0 operates normally 1: ftiob0 operates in pwm mode 13.3.4 timer function control register (tfcr) tfcr selects the settings and output levels for each operating mode. bit bit name initial value r/w description 7 ? 1 ? reserved this bit is always read as 1. 6 stclk 0 r/w external clock input select 0: external clock input is disabled 1: external clock input is enabled 5 adeg 0 r/w a/d trigger edge select a/d module should be set to start an a/d conversion by the external trigger 0: a/d trigger at the crest in complementary pwm mode 1: a/d trigger at the trough in complementary pwm mode 4 adtrg 0 r/w external trigger disable 0: a/d trigger for pwm cycles is disabled in complementary pwm mode 1: a/d trigger for pwm cycles is enabled in complementary pwm mode
section 13 timer z rev. 3.00 sep. 10, 2007 page 209 of 528 rej09b0216-0300 bit bit name initial value r/w description 3 ols1 0 r/w output level select 1 selects the counter-phase output levels in reset synchronous pwm mode or complementary pwm mode. 0: initial output is high and the active level is low. 1: initial output is low and the active level is high. 2 ols0 0 r/w output level select 0 selects the normal-phase output levels in reset synchronous pwm mode or complementary pwm mode. 0: initial output is high and the active level is low. 1: initial output is low and the active level is high. figure 13.4 shows an example of outputs in reset synchronous pwm mode and complementary pwm mode when ols1 = 0 and ols0 = 0. 1 0 cmd1 cmd0 0 0 r/w r/w combination mode 1 and 0 00: channel 0 and channel 1 operate normally 01: channel 0 and channel 1 are used together to operate in reset synchronous pwm mode 10: channel 0 and channel 1 are used together to operate in complementary pwm mode (transferred at the trough) 11: channel 0 and channel 1 are used together to operate in complementary pwm mode (transferred at the crest) note: when reset synchronous pwm mode or complementary pwm mode is selected by these bits, this setting has the priority to the settings for pwm mode by each bit in tpmr. stop tcnt_0 and tcnt_1 before making settings for reset synchronous pwm mode or complementary pwm mode.
section 13 timer z rev. 3.00 sep. 10, 2007 page 210 of 528 rej09b0216-0300 tcnt_0 normal phase counter phase normal phase counter phase active level active level active level active level complementary pwm mode note: write h'00 to tocr to start initial outputs after stopping the counter. reset synchronous pwm mode initial output initial output tcnt_1 figure 13.4 example of outputs in reset synchronous pwm mode and complementary pwm mode 13.3.5 timer output master enable register (toer) toer enables/disables the outputs for channel 0 and channel 1. when wkp4 is selected for inputs, if a low level signal is input to wkp4 , the bits in toer are set to 1 to disable the output for timer z. bit bit name initial value r/w description 7 ed1 1 r/w master enable d1 0: ftiod1 pin output is enabled according to the tpmr, tfcr, and tiorc_1 settings 1: ftiod1 pin output is disabled regardless of the tpmr, tfcr, and tiorc_1 settings (ftiod1 pin is operated as an i/o port). 6 ec1 1 r/w master enable c1 0: ftioc1 pin output is enabled according to the tpmr, tfcr, and tiorc_1 settings 1: ftioc1 pin output is disabled regardless of the tpmr, tfcr, and tiorc_1 settings (ftioc1 pin is operated as an i/o port).
section 13 timer z rev. 3.00 sep. 10, 2007 page 211 of 528 rej09b0216-0300 bit bit name initial value r/w description 5 eb1 1 r/w master enable b1 0: ftiob1 pin output is enabled according to the tpmr, tfcr, and tiora_1 settings 1: ftiob1 pin output is disabled regardless of the tpmr, tfcr, and tiora_1 settings (ftiob1 pin is operated as an i/o port). 4 ea1 1 r/w master enable a1 0: ftioa1 pin output is enabled according to the tpmr, tfcr, and tiora_1 settings 1: ftioa1 pin output is disabled regardless of the tpmr, tfcr, and tiora_1 settings (ftioa1 pin is operated as an i/o port). 3 ed0 1 r/w master enable d0 0: ftiod0 pin output is enabled according to the tpmr, tfcr, and tiorc_0 settings 1: ftiod0 pin output is disabled regardless of the tpmr, tfcr, and tiorc_0 settings (ftiod0 pin is operated as an i/o port). 2 ec0 1 r/w master enable c0 0: ftioc0 pin output is enabled according to the tpmr, tfcr, and tiorc_0 settings 1: ftioc0 pin output is disabled regardless of the tpmr, tfcr, and tiorc_0 settings (ftioc0 pin is operated as an i/o port). 1 eb0 1 r/w master enable b0 0: ftiob0 pin output is enabled according to the tpmr, tfcr, and tiora_0 settings 1: ftiob0 pin output is disabled regardless of the tpmr, tfcr, and tiora_0 settings (ftiob0 pin is operated as an i/o port). 0 ea0 1 r/w master enable a0 0: ftioa0 pin output is enabled according to the tpmr, tfcr, and tiora_0 settings 1: ftioa0 pin output is disabled regardless of the tpmr, tfcr, and tiora_0 settings (ftioa0 pin is operated as an i/o port).
section 13 timer z rev. 3.00 sep. 10, 2007 page 212 of 528 rej09b0216-0300 13.3.6 timer output control register (tocr) tocr selects the initial outputs before the first occurrence of a compare match. note that bits ols1 and ols0 in tfcr set these initial outputs in reset synchronous pwm mode and complementary pwm mode. bit bit name initial value r/w description 7 tod1 0 r/w output level select d1 0: 0 output at the ftiod1 pin * 1: 1 output at the ftiod1 pin * 6 toc1 0 r/w output level select c1 0: 0 output at the ftioc1 pin * 1: 1 output at the ftioc1 pin * 5 tob1 0 r/w output level select b1 0: 0 output at the ftiob1 pin * 1: 1 output at the ftiob1 pin * 4 toa1 0 r/w output level select a1 0: 0 output at the ftioa1 pin * 1: 1 output at the ftioa1 pin * 3 tod0 0 r/w output level select d0 0: 0 output at the ftiod0 pin * 1: 1 output at the ftiod0 pin * 2 toc0 0 r/w output level select c0 0: 0 output at the ftioc0 pin * 1: 1 output at the ftioc0 pin * 1 tob0 0 r/w output level select b0 0: 0 output at the ftiob0 pin * 1: 1 output at the ftiob0 pin * 0 toa0 0 r/w output level select a0 0: 0 output at the ftioa0 pin * 1: 1 output at the ftioa0 pin * note: * the change of the setting is immediately reflected in the output value.
section 13 timer z rev. 3.00 sep. 10, 2007 page 213 of 528 rej09b0216-0300 13.3.7 timer counter (tcnt) the timer z has two tcnt counters (tcnt_0 and tcnt_1), one for each channel. the tcnt counters are 16-bit readable/writabl e registers that increment/decr ement according to input clocks. input clocks can be selected by bits tpsc2 to tpsc0 in tcr. tcnt0 and tcnt 1 increment/decremen t in complementary pwm mode, while they only increment in other modes. the tcnt counters are initialized to h'0000 by compare matches with corresponding gra, grb, grc, or grd, or input captures to gra, grb, grc, or grd (counter clearing function). when the tcnt counters overflow, an ovf flag in tsr for the corresponding channel is set to 1. when tcnt_1 underflows, an udf flag in tsr is set to 1. the tcnt counters cannot be accessed in 8- bit units; they must always be accessed as a 16-bit unit. tcnt is initialized to h'0000. 13.3.8 general registers a, b, c, and d (gra, grb, grc, and grd) gr are 16-bit registers. timer z has eight general registers (gr), four for each channel. the gr registers are dual function 16-bit readable/writable registers, functioning as either output compare or input capture registers. functions can be switched by tiora and tiorc. the values in gr and tcnt are constantly compar ed with each other when the gr registers are used as output compare registers. when the both values match, the imfa to imfd flags in tsr are set to 1. compare match outputs can be selected by tiora and tiorc. when the gr registers are used as input capture registers, the tcnt value is stored after detecting external signals. at this point, imfa to imfd flags in the corresponding tsr are set to 1. detection edges for input capture signals can be selected by tiora and tiorc. when pwm mode, complementary pwm mode, or reset synchronous pwm mode is selected, the values in tiora and tiorc are ignored. upon reset, the gr registers are set as output compare registers (no output) and initiali zed to h'ffff. the gr registers cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit.
section 13 timer z rev. 3.00 sep. 10, 2007 page 214 of 528 rej09b0216-0300 13.3.9 timer control register (tcr) the tcr registers select a tcnt counter clock, an edge when an external clock is selected, and counter clearing sources. timer z has a total of two tcr registers, one for each channel. bit bit name initial value r/w description 7 6 5 cclr2 cclr1 cclr0 0 0 0 r/w r/w r/w counter clear 2 to 0 000: disables tcnt clearing 001: clears tcnt by gra compare match/input capture * 1 010: clears tcnt by grb compare match/input capture * 1 011: synchronization clear; clears tcnt in synchronous with counter clearing of the other channel?s timer * 2 100: disables tcnt clearing 101: clears tcnt by grc compare match/input capture * 1 110: clears tcnt by grd compare match/input capture * 1 111: synchronization clear; clears tcnt in synchronous with counter clearing of the other channel?s timer * 2 4 3 ckeg1 ckeg0 0 0 r/w r/w clock edge 1 and 0 00: count at rising edge 01: count at falling edge 1x: count at both edges 2 1 0 tpsc2 tpsc1 tpsc0 0 0 0 r/w r/w r/w time prescaler 2 to 0 000: internal clock: count by 001: internal clock: count by /2 010: internal clock: count by /4 011: internal clock: count by /8 1xx: external clock: count by ftioa0 (tclk) pin input notes: 1. when gr functions as an output compare register, tcnt is cleared by compare match. when gr functions as input capture, tcnt is cleared by input capture. 2. synchronous operation is set by tmdr. 3. x: don?t care
section 13 timer z rev. 3.00 sep. 10, 2007 page 215 of 528 rej09b0216-0300 13.3.10 timer i/o control register (tiora and tiorc) the tior registers control the general registers (gr). timer z has four tior registers (tiora_0, tiora_1, tiorc_0, and tiorc_1), tw o for each channel. in pwm mode including complementary pwm mode and reset synchronous pwm mode, the settings of tior are invalid. tiora: tiora selects whether gra or grb is used as an output compare register or an input capture register. when an output compare register is selected, the output se tting is selected. when an input capture register is selected, an input edge of an input capture signal is selected. tiora also selects the function of ftioa or ftiob pin. bit bit name initial value r/w description 7 ? 1 ? reserved this bit is always read as 1. 6 5 4 iob2 iob1 iob0 0 0 0 r/w r/w r/w i/o control b2 to b0 grb is an output compare register: 000: disables pin output by compare match 001: 0 output by grb compare match 010: 1 output by grb compare match 011: toggle output by grb compare match grb is an input capture register: 100: input capture to grb at the rising edge 101: input capture to grb at the falling edge 11x: input capture to grb at both rising and falling edges 3 ? 1 ? reserved this bit is always read as 1.
section 13 timer z rev. 3.00 sep. 10, 2007 page 216 of 528 rej09b0216-0300 bit bit name initial value r/w description 2 1 0 ioa2 ioa1 ioa0 0 0 0 r/w r/w r/w i/o control a2 to a0 gra is an output compare register: 000: disables pin output by compare match 001: 0 output by gra compare match 010: 1 output by gra compare match 011: toggle output by gra compare match gra is an input capture register: 100: input capture to gra at the rising edge 101: input capture to gra at the falling edge 11x: input capture to gra at both rising and falling edges [legend] x: don't care. tiorc: tiorc selects whether grc or grd is used as an output compare register or an input capture register. when an output compare register is selected, the output se tting is selected. when an input capture register is selected, an input edge of an input capture signal is selected. tiorc also selects the function of ftioc or ftiod pin. bit bit name initial value r/w description 7 ? 1 ? reserved this bit is always read as 1. 6 5 4 iod2 iod1 iod0 0 0 0 r/w r/w r/w i/o control d2 to d0 grd is an output compare register: 000: disables pin output by compare match 001: 0 output by grd compare match 010: 1 output by grd compare match 011: toggle output by grd compare match grd is an input capture register: 100: input capture to grd at the rising edge 101: input capture to grd at the falling edge 11x: input capture to grd at both rising and falling edges 3 ? 1 ? reserved this bit is always read as 1.
section 13 timer z rev. 3.00 sep. 10, 2007 page 217 of 528 rej09b0216-0300 bit bit name initial value r/w description 2 1 0 ioc2 ioc1 ioc0 0 0 0 r/w r/w r/w i/o control c2 to c0 grc is an output compare register: 000: disables pin output by compare match 001: 0 output by grc compare match 010: 1 output by grc compare match 011: toggle output by grc compare match grc is an input capture register: 100: input capture to grc at the rising edge 101: input capture to grc at the falling edge 11x: input capture to grc at both rising and falling edges [legend] x: don't care.
section 13 timer z rev. 3.00 sep. 10, 2007 page 218 of 528 rej09b0216-0300 13.3.11 timer status register (tsr) tsr indicates generation of an overflow/underflow of tcnt and a compare match/input capture of gra, grb, grc, and grd. these flags are in terrupt sources. if an interrupt is enabled by a corresponding bit in tier, tsr requests an interrupt for the cpu. timer z has two tsr registers, one for each channel. bit bit name initial value r/w description 7, 6 ? all 1 ? reserved these bits are always read as 1. 5 udf * 0 r/w underflow flag [setting condition] ? when tcnt_1 underflows [clearing condition] ? when 0 is written to udf after reading udf = 1 4 ovf 0 r/w overflow flag [setting condition] ? when the tcnt value underflows [clearing condition] ? when 0 is written to ovf after reading ovf = 1 3 imfd 0 r/w input capture/compare match flag d [setting conditions] ? when tcnt = grd and grd is functioning as output compare register ? when tcnt value is transferred to grd by input capture signal and grd is functioning as input capture register [clearing condition] ? when 0 is written to imfd after reading imfd = 1
section 13 timer z rev. 3.00 sep. 10, 2007 page 219 of 528 rej09b0216-0300 bit bit name initial value r/w description 2 imfc 0 r/w input capture/compare match flag c [setting conditions] ? when tcnt = grc and grc is functioning as output compare register ? when tcnt value is transferred to grc by input capture signal and grc is functioning as input capture register [clearing condition] ? when 0 is written to imfc after reading imfc = 1 1 imfb 0 r/w input capture/compare match flag b [setting conditions] ? when tcnt = grb and grb is functioning as output compare register ? when tcnt value is transferred to grb by input capture signal and grb is functioning as input capture register [clearing condition] ? when 0 is written to imfb after reading imfb = 1 0 imfa 0 r/w input capture/compare match flag a [setting conditions] ? when tcnt = gra and gra is functioning as output compare register ? when tcnt value is transferred to gra by input capture signal and gra is functioning as input capture register [clearing condition] ? when 0 is written to imfa after reading imfa = 1 note: bit 5 is not the udf flag in tsr_0. it is a reserved bit. it is always read as 1.
section 13 timer z rev. 3.00 sep. 10, 2007 page 220 of 528 rej09b0216-0300 13.3.12 timer interrupt enable register (tier) tier enables or disables interrupt requests fo r overflow or gr comp are match/input capture. timer z has two tier registers, one for each channel. bit bit name initial value r/w description 7 to 5 ? all 1 ? reserved these bits are always read as 1. 4 ovie 0 r/w overflow interrupt enable 0: interrupt requests (ovi) by ovf or udf flag are disabled 1: interrupt requests (ovi) by ovf or udf flag are enabled 3 imied 0 r/w input capture/compare match interrupt enable d 0: interrupt requests (imid) by imfd flag are disabled 1: interrupt requests (imid) by imfd flag are enabled 2 imiec 0 r/w input capture/compare match interrupt enable c 0: interrupt requests (imic) by imfc flag are disabled 1: interrupt requests (imic) by imfc flag are enabled 1 imieb 0 r/w input capture/compare match interrupt enable b 0: interrupt requests (imib) by imfb flag are disabled 1: interrupt requests (imib) by imfb flag are enabled 0 imiea 0 r/w input capture/compare match interrupt enable a 0: interrupt requests (imia) by imfa flag are disabled 1: interrupt requests (imia) by imfa flag are enabled
section 13 timer z rev. 3.00 sep. 10, 2007 page 221 of 528 rej09b0216-0300 13.3.13 pwm mode output level control register (pocr) pocr control the active level in pwm mode. timer z has two pocr registers, one for each channel. bit bit name initial value r/w description 7 to 3 ? all 1 ? reserved these bits are always read as 1. 2 pold 0 r/w pwm mode output level control d 0: the output level of ftiod is low-active 1: the output level of ftiod is high-active 1 polc 0 r/w pwm mode output level control c 0: the output level of ftioc is low-active 1: the output level of ftioc is high-active 0 polb 0 r/w pwm mode output level control b 0: the output level of ftiob is low-active 1: the output level of ftiob is high-active
section 13 timer z rev. 3.00 sep. 10, 2007 page 222 of 528 rej09b0216-0300 13.3.14 interface with cpu 1. 16-bit register tcnt and gr are 16-bit registers. reading/writing in a 16-bit unit is enabled but disabled in an 8-bit unit since the data bus with the cpu is 16-bit width. these registers must always be accessed in a 16-bit unit. figure 13.5 shows an example of accessing the 16-bit registers. h internal data bus bus interface module data bus c p u l tcntl tcnth figure 13.5 accessing operation of 16-bit register (between cpu and tcnt (16 bits)) 2. 8-bit register registers other than tcnt and gr are 8-bit regi sters that are connected internally with the cpu in an 8-bit width. figure 13.6 shows an example of accessing the 8-bit registers. tstr h internal data bus bus interface module data bus c p u l figure 13.6 accessing operation of 8-bit register (between cpu and tstr (8 bits))
section 13 timer z rev. 3.00 sep. 10, 2007 page 223 of 528 rej09b0216-0300 13.4 operation 13.4.1 counter operation when one of bits str0 and str1 in tstr is set to 1, the tcnt counter for the corresponding channel begins counting. tcnt can operate as a free-running counter, periodic counter, for example. figure 13.7 shows an example of the counter operation setting procedure. [1] select the counter clock with bits tpsc2 to tpsc0 in tcr. when an external clock is selected, select the external clock edge with bits ckeg1 and ckeg0 in tcr. [2] for periodic counter operation, select the tcnt clearing source with bits cclr2 to cclr0 in tcr. [3] designate the general register selected in [2] as an output compare register by means of tior. [4] set the periodic counter cycle in the general register selected in [2]. [5] set the str bit in tstr to 1 to start the counter operation. operation selection periodic counter free-running counter [1] select counter clock [2] select counter clearing source [3] select output compare register [5] start count operation [4] set period figure 13.7 example of count er operation setting procedure
section 13 timer z rev. 3.00 sep. 10, 2007 page 224 of 528 rej09b0216-0300 1. free-running count operation and periodic count operation immediately after a reset, the tcnt counters for channels 0 and 1 are all designated as free- running counters. when the relevant bit in tstr is set to 1, the corresponding tcnt counter starts an increment operation as a free-running counter. when tcnt overflows, the ovf flag in tsr is set to 1. if the value of the ovie bit in the corresponding tier is 1 at this point, timer z requests an interrupt. after overflow, tcnt starts an increment operation again from h'0000. figure 13.8 illustrates free-running counter operation. h'ffff tcnt value time h'0000 str0, str1 ovf figure 13.8 free-running counter operation when compare match is selected as the tcnt clearing source, the tcnt counter for the relevant channel performs periodic count operation. the gr registers for setting the period are designated as output compare registers, and counter clearing by compare match is selected by means of bits cclr1 and cclr0 in tcr. after the settings have been made, tcnt starts an increment operation as a periodic counter when the corresponding bit in tstr is set to 1. when the count value matches the value in gr, the imfa, imfb, imfc, or imfd flag in tsr is set to 1 and tcnt is cleared to h'0000. if the value of the corresponding imiea, imieb, imiec, or imied bit in tier is 1 at this point, the timer z requests an interrupt. after a comp are match, tcnt starts an increment operation again from h'0000. figure 13.9 illustrates peri odic counter operation.
section 13 timer z rev. 3.00 sep. 10, 2007 page 225 of 528 rej09b0216-0300 h'0000 time counter cleared by gr compare match str gr value tcnt value imf figure 13.9 period ic counter operation 2. tcnt count timing a. internal clock operation a system clock ( ) or three types of clocks ( /2, /4, or /8) that divides the system clock can be selected by bits tpsc2 to tpsc0 in tcr. figure 13.10 illustrates this timing. tcnt tcnt input internal clock n-1 n n+1 figure 13.10 count timing at internal clock operation
section 13 timer z rev. 3.00 sep. 10, 2007 page 226 of 528 rej09b0216-0300 b. external clock operation an external clock input pin (tclk) can be selected by bits tpsc2 to tpsc0 in tcr, and a detection edge can be selected by bits ckeg1 and ckeg0. to detect an external clock, the rising edge, falling edge, or both edges can be selected. the pulse width of the external clock needs two or more system clocks. note that an external clock does not operate correctly with the lower pulse width. figure 13.11 illustrates the detection timing of the rising and falling edges. tcnt external clock input pin tcnt input n-1 n n+1 figure 13.11 count timing at external clock operation (both edges detected)
section 13 timer z rev. 3.00 sep. 10, 2007 page 227 of 528 rej09b0216-0300 13.4.2 waveform output by compare match timer z can perform 0, 1, or toggle output from the corresponding ftioa, ftiob, ftioc, or ftiod output pin using compare match a, b, c, or d. figure 13.12 shows an example of the setting procedure for waveform output by compare match. [1] select 0 output, 1 output, or toggle output as a compare much output, by means of tior. the initial values set in tocr are output unit the first compare match occurs. [2] set the timing for compare match generation in gra/grb/grc/grd. [3] enable or disable the timer output by toer. [4] set the str bit in tstr to 1 to start the tcnt count operation. [1] output selection select waveform output mode [2] set output timing [3] enable waveform output [4] start count operation figure 13.12 example of setting procedure for waveform output by compare match 1. examples of waveform output operation figure 13.13 shows an example of 0 output/1 output. in this example, tcnt has been designated as a free-running counter, and settings have been made such that 0 is output by compare match a, and 1 is output by compare match b. when the set level and the pin level coincide, the pin level does not change.
section 13 timer z rev. 3.00 sep. 10, 2007 page 228 of 528 rej09b0216-0300 h'ffff h'0000 ftiob time no change no change no change no change tcnt value ftioa figure 13.13 example of 0 output/1 output operation figure 13.14 shows an example of toggle output. in this example, tcnt has been designated as a periodic counter (with counter clearing on compare match b), and settings have been made such that the output is toggled by both compare match a and compare match b. grb gra h'0000 ftiob toggle output toggle output time tcnt value ftioa figure 13.14 example of toggle output operation
section 13 timer z rev. 3.00 sep. 10, 2007 page 229 of 528 rej09b0216-0300 2. output compare timing the compare match signal is generated in the last state in which tcnt and gr match (when tcnt changes from the matching value to the next value). when the compare match signal is generated, the output value selected in tior is output at the compare match output pin (ftioa, ftiob, ftioc, or ftiod). when tcnt matches gr, the compare match signal is generated only after the next tcnt input clock pulse is input. figure 13.15 shows an example of the output compare timing. tcnt ftioa to ftiod compare match signal tcnt input gr n n n+1 figure 13.15 output compare timing 13.4.3 input capture function the tcnt value can be transferred to gr on detection of the input edge of the input capture/output compare pin (ftioa, ftiob, ftioc, or ftiod). rising edge, falling edge, or both edges can be selected as the detected edge. when the input capture function is used, the pulse width or period can be measured. figure 13.16 shows an example of the input capture operation setting procedure.
section 13 timer z rev. 3.00 sep. 10, 2007 page 230 of 528 rej09b0216-0300 [1] designate gr as an input capture register by means of tior, and select rising edge, falling edge, or both edges as the input edge of the input capture signal. [2] set the str bit in tstr to 1 to start the tcnt counter operation. [1] input selection select input edge of input capture [2] start counter operation figure 13.16 example of input capture operation setting procedure
section 13 timer z rev. 3.00 sep. 10, 2007 page 231 of 528 rej09b0216-0300 1. example of input capture operation figure 13.17 shows an example of input capture operation. in this example, both rising and falling edges have been selected as the ftioa pin input capture input edge, the falling edge has been se lected as the ftiob pin input capture input edge, and counter clearing by grb input capture has been designated for tcnt. ftioa tcnt value counter cleared by ftiob input (falling edge) time ftiob gra h'0005 h'0005 h'0000 h'0160 h'0160 grb h'0180 h'0180 figure 13.17 example of input capture operation
section 13 timer z rev. 3.00 sep. 10, 2007 page 232 of 528 rej09b0216-0300 2. input capture signal timing input capture on the rising edge, falling edge, or both edges can be select ed through settings in tior. figure 13.18 shows the timing when the rising edge is selected. the pulse width of the input capture signal must be at least two system clock ( ) cycles. tcnt input capture signal input capture input gr n n figure 13.18 input capture signal timing
section 13 timer z rev. 3.00 sep. 10, 2007 page 233 of 528 rej09b0216-0300 13.4.4 synchronous operation in synchronous operation, the values in a number of tcnt counters can be rewritten simultaneously (synchronous presetting). also, a number of tcnt counters can be cleared simultaneously by making the appropriate setting in tcr (synchronous clearing). synchronous operation enables gr to be increased with respect to a single time base. figure 13.19 shows an example of the synchronous operation setting procedure. no yes synchronous operation selection clearing source generation channel? set synchronous operation select counter clearing source synchronous presetting set tcnt synchronous clearing [1] [2] [3] select counter clearing source [4] start counter operation [5] start counter operation [5] [1] set the sync bits in tmdr to 1. [2] when a value is written to either of the tcnt counters, the same value is simultaneously written to the other tcnt counter. [3] set bits cclr1 and cclr0 in tcr to specify counter clearing by compare match/input capture. [4] set bits cclr1 and cclr0 in tcr to designate synchronous clearing for the counter clearing source. [5] set the str bit in tstr to 1 to start the count operation. figure 13.19 example of synchronous operation setting procedure
section 13 timer z rev. 3.00 sep. 10, 2007 page 234 of 528 rej09b0216-0300 figure 13.20 shows an example of synchronous operation. in this example, synchronous operation has been selected, ftiob0 and ftiob1 have been designated for pwm mode, gra_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 counter clearing source. in addition, the same input clock has been set as the counter input clock for channel 0 and channel 1. two-phase pwm waveforms are output from pins ftiob0 and ftiob1. at this time, sync hronous presetting and synchronous operation by gra_0 compare match are performed by tcnt counters. for details on pwm mode, see section 13.4.5, pwm mode. gra_0 time synchronous clearing by gra_0 compare match tcnt values gra_1 grb_0 grb_1 h'0000 ftiob0 ftiob1 figure 13.20 example of synchronous operation 13.4.5 pwm mode in pwm mode, pwm waveforms are output from the ftiob, ftioc, and ftiod output pins with gra as a cycle register and grb, grc, a nd grd as duty registers. the initial output level of the corresponding pin depends on the setting values of tocr and pocr. table 13.3 shows an example of the initial output level of the ftiob0 pin. the output level is determined by the polb to pold bits corresponding to pocr. when polb is 0, the ftiob output pin is set to 0 by compare match b and set to 1 by compare match a. when polb is 1, the ftiob output pin is set to 1 by compare match b and cleared to 0 by compare match a. in pwm mode, maximum 6-phase pwm outputs are possible. figure 13.21 shows an example of the pwm mode setting procedure.
section 13 timer z rev. 3.00 sep. 10, 2007 page 235 of 528 rej09b0216-0300 table 13.3 initial output level of ftiob0 pin tob0 polb initial output level 0 0 1 0 1 0 1 0 0 1 1 1 [1] select the counter clock with bits tpsc2 to tosc0 in tcr. when an external clock is selected, select the external clock edge with bits ckeg1 and ckeg0 in tcr. [2] use bits cclr1 and cclr0 in tcr to select the counter clearing source. [3] select the pwm mode with bits pwmb0 to pwmd0 and pwmb1 to pwmd1 in tpmr. [4] set the initial output value with bits tob0 to tod0 and tob1 to tod1 in tocr. [5] set the output level with bits polb to pold in pocr. [6] set the cycle in gra, and set the duty in the other gr. [7] enable or disable the timer output by toer. [8] set the str bit in tstr to 1 and start the counter operation. [1] [2] [3] [4] [5] [6] [7] pwm mode select counter clock select counter clearing source set pwm mode set initial output level select output level set gr enable waveform output [8] start counter operation figure 13.21 example of pwm mode setting procedure
section 13 timer z rev. 3.00 sep. 10, 2007 page 236 of 528 rej09b0216-0300 figure 13.22 shows an example of operation in pwm mode. the output signals go to 1 and tcnt is reset at compare match a, and the output signa ls go to 0 at compare match b, c, and d (tob, toc, and tod = 0, polb, polc, and pold = 0). gra tcnt value time counter cleared by gra compare match grb grc grd h'0000 ftioc ftiod ftiob figure 13.22 example of pwm mode operation (1)
section 13 timer z rev. 3.00 sep. 10, 2007 page 237 of 528 rej09b0216-0300 figure 13.23 shows another example of operation in pwm mode. the output signals go to 0 and tcnt is reset at compare match a, and the output signals go to 1 at compare match b, c, and d (tob, toc, and tod = 0, polb, polc, and pold = 1). gra grb grc grd h'0000 ftioc ftiod ftiob counter cleared by gra compare match time tcnt value figure 13.23 example of pwm mode operation (2) figures 13.24 (when tob, toc, and tod = 0, polb, polc, and pold = 0) and 13.25 (when tob, toc, and tod = 0, polb, polc, and pold = 1) show examples of the output of pwm waveforms with duty cycles of 0% and 100% in pwm mode.
section 13 timer z rev. 3.00 sep. 10, 2007 page 238 of 528 rej09b0216-0300 gra tcnt value 0% duty 0% duty time time time grb rewritten tcnt value grb rewritten grb rewritten grb rewritten tcnt value grb rewritten grb rewritten grb rewritten when cycle register and duty register compare matches occur simultaneously, duty register compare match has priority. when cycle register and duty register compare matches occur simultaneously, duty register compare match has priority. grb rewritten 100% duty 100% duty grb h'0000 ftiob gra grb h'0000 ftiob gra grb h'0000 ftiob figure 13.24 example of pwm mode operation (3)
section 13 timer z rev. 3.00 sep. 10, 2007 page 239 of 528 rej09b0216-0300 gra grb h'0000 ftiob gra grb h'0000 ftiob gra grb h'0000 ftiob tcnt value 0% duty time grb rewritten grb rewritten time tcnt value grb rewritten grb rewritten grb rewritten 100% duty 0% duty time tcnt value grb rewritten grb rewritten grb rewritten 100% duty when cycle register and duty register compare matches occur simultaneously, duty register compare match has priority. when cycle register and duty register compare matches occur simultaneously, duty register compare match has priority. figure 13.25 example of pwm mode operation (4)
section 13 timer z rev. 3.00 sep. 10, 2007 page 240 of 528 rej09b0216-0300 13.4.6 reset synchronous pwm mode three normal- and counter-phase pwm waveforms are output by combining channels 0 and 1 that one of changing points of waveforms will be common. in reset synchronous pwm mode, the ftiob0 to ftiod0 and ftioa1 to ftiod1 pins become pwm-output pins automatically. tcnt_0 performs an increment operation. tables 13.4 and 13.5 show the pwm-output pins used and the register settings, respectively. figure 13.26 shows the example of reset synchronous pwm mode setting procedure. table 13.4 output pins in reset synchronous pwm mode channel pin name input/output pin function 0 ftioc0 output toggle output in synchronous with pwm cycle 0 ftiob0 output pwm output 1 0 ftiod0 output pwm output 1 (counter-phase waveform of pwm output 1) 1 ftioa1 output pwm output 2 1 ftioc1 output pwm output 2 (counter-phase waveform of pwm output 2) 1 ftiob1 output pwm output 3 1 ftiod1 output pwm output 3 (counter-phase waveform of pwm output 3) table 13.5 register settings in reset synchronous pwm mode register description tcnt_0 initial setting of h'0000 tcnt_1 not used (independently operates) gra_0 sets counter cycle of tcnt_0 grb_0 set a changing point of the pwm waveform output from pins ftiob0 and ftiod0. gra_1 set a changing point of the pwm waveform output from pins ftioa1 and ftioc1. grb_1 set a changing point of the pwm waveform output from pins ftiob1 and ftiod1.
section 13 timer z rev. 3.00 sep. 10, 2007 page 241 of 528 rej09b0216-0300 [1] clear bit str0 in tstr to 0 and stop the counter operation of tcnt_0. set reset synchronous pwm mode after tcnt_0 stops. [2] select the counter clock with bits tpsc2 to tosc0 in tcr. when an external clock is selected, select the external clock edge with bits ckeg1 and ckeg0 in tcr. [3] use bits cclr1 and cclr0 in tcr to select counter clearing source gra_0. [4] select the reset synchronous pwm mode with bits cmd1 and cmd0 in tfcr. ftiob0 to ftiod0 and ftioa1 to ftiod1 become pwm output pins automatically. [5] set h'00 to tocr. [6] set tcnt_0 as h'0000. tcnt1 does not need to be set. [7] gra_0 is a cycle register. set a cycle for gra_0. set the changing point timing of the pwm output waveform for grb_0, gra_1, and grb_1. [8] enable or disable the timer output by toer. [9] set the str bit in tstr to 1 and start the counter operation. [1] reset synchronous pwm mode [2] stop counter operation [3] select counter clock [4] select counter clearing source [5] set reset synchronous pwm mode [6] initialize the output pin [7] set tcnt [8] set gr [9] start counter operation enable waveform output figure 13.26 example of reset synchronous pwm mode setting procedure
section 13 timer z rev. 3.00 sep. 10, 2007 page 242 of 528 rej09b0216-0300 figures 13.27 and 13.28 show examples of operation in reset synchronous pwm mode. gra_0 tcnt value counter cleared by gra compare match time grb_0 gra_1 grb_1 h'0000 ftioa1 ftiob1 ftiob0 ftioc1 ftiod1 ftioc0 ftiod0 figure 13.27 example of reset synchronous pwm mode operation (ols0 = ols1 = 1)
section 13 timer z rev. 3.00 sep. 10, 2007 page 243 of 528 rej09b0216-0300 gra_0 grb_0 gra_1 grb_1 h'0000 ftioa1 ftiob1 ftiob0 ftioc1 ftiod1 ftioc0 ftiod0 tcnt value counter cleared by gra compare match time figure 13.28 example of reset synchronous pwm mode operation (ols0 = ols1 = 0) in reset synchronous pwm mode, tcnt_0 and tcnt_1 perform increment and independent operations, respectively. however, gra_1 and grb_1 are separated from tcnt_1. when a compare match occurs between tcnt_0 and gra _0, a counter is clear ed and an increment operation is restarted from h'0000. the pwm pin outputs 0 or 1 whenever a compare match between grb_0, gra_1, grb_1 and tcnt_0 or counter clearing occur. for details on operations when reset synchronous pwm mode and buffer operation are simultaneously set, refer to section 13.4.8, buffer operation.
section 13 timer z rev. 3.00 sep. 10, 2007 page 244 of 528 rej09b0216-0300 13.4.7 complementary pwm mode three pwm waveforms for non-overlapped normal and counter phases are output by combining channels 0 and 1. in complementary pwm mode, the ftiob0 to ftiod0 and ftioa1 to ftiod1 pins become pwm-output pins automatically. tcnt_0 and tcnt_1 perform an increment or decrement operation. tables 13.6 and 13.7 show the output pins and register settings in complementary pwm mode, respectively. figure 13.29 shows the example of complementary pwm mode setting procedure. table 13.6 output pins in complementary pwm mode channel pin name input/output pin function 0 ftioc0 output toggle output in synchronous with pwm cycle 0 ftiob0 output pwm output 1 0 ftiod0 output pwm output 1 (counter-phase waveform non- overlapped with pwm output 1) 1 ftioa1 output pwm output 2 1 ftioc1 output pwm output 2 (counter-phase waveform non- overlapped with pwm output 2) 1 ftiob1 output pwm output 3 1 ftiod1 output pwm output 3 (counter-phase waveform non- overlapped with pwm output 3) table 13.7 register settings in complementary pwm mode register description tcnt_0 initial setting of non-overlapped periods (non-overlapped periods are differences with tcnt_1) tcnt_1 initial setting of h'0000 gra_0 sets (upper limit value ? 1) of tcnt_0 grb_0 set a changing point of the pwm waveform output from pins ftiob0 and ftiod0. gra_1 set a changing point of the pwm waveform output from pins ftioa1 and ftioc1. grb_1 set a changing point of the pwm waveform output from pins ftiob1 and ftiod1.
section 13 timer z rev. 3.00 sep. 10, 2007 page 245 of 528 rej09b0216-0300 [1] clear bits str0 and str1 in tstr to 0, and stop the counter operation of tcnt_0. stop tcnt_0 and tcnt_1 and set complementary pwm mode. [2] write h'00 to tocr. [3] use bits tpsc2 to tpsc0 in tcr to select the same counter clock for channels 0 and 1. when an external clock is selected, select the edge of the external clock by bits ckeg1 and ckeg0 in tcr. do not use bits cclr1 and cclr0 in tcr to clear the counter. [4] use bits cmd1 and cmd0 in tfcr to set complementary pwm mode. ftiob0 to ftiod0 and ftioa1 to ftiod1 automatically become pwm output pins. [5] set h'00 to tocr. [6] tcnt_1 must be h'0000. set a non- overlapped period to tcnt_0. [7] gra_0 is a cycle register. set the cycle to gra_0. set the timing to change the pwm output waveform to grb_0, gra_1, and grb_1. note that the timing must be set within the range of compare match carried out for tcnt_0 and tcnt_1. for gr settings, see 3. setting gr value in complementary pwm mode in section 13.4.7, complementary pwm mode. [8] use toer to enable or disable the timer output. [9] set the str0 and str1 bits in tstr to 1 to start the count operation. [1] complementary pwm mode stop counter operation note: to re-enter complementary pwm mode, first, enter a mode other than the complementary pwm mode. after that, repeat the setting procedures from step [1]. for settings of waveform outputs with a duty cycle of 0% and 100%, see the settings shown in 2. examples of complementary pwm mode operation and 3. setting gr value in complementary pwm mode in section 13.4.7, complementary pwm mode. [2] initialize output pin [3] select counter clock [4] set complementary pwm mode [5] initialize output pin [6] set tcnt [7] set gr [8] enable waveform output [9] start counter operation figure 13.29 example of complementary pwm mode setting procedure
section 13 timer z rev. 3.00 sep. 10, 2007 page 246 of 528 rej09b0216-0300 1. canceling procedure of complementary pwm mode: figure 13.30 shows the complementary pwm mode canceling procedure. [1] clear bit cmd1 in tfcr to 0, and set channels 0 and 1 to normal operation. [2] after setting channels 0 and 1 to normal operation, clear bits str0 and str1 in tstr to 0 and stop tcnt0 and tcnt1. [1] [2] complementary pwm mode stop counter operation cancel complementary pwm mode figure 13.30 canceling procedure of complementary pwm mode
section 13 timer z rev. 3.00 sep. 10, 2007 page 247 of 528 rej09b0216-0300 2. examples of complementary pwm mode operation: figure 13.31 shows an example of complementary pwm mode operation. in complementary pwm mode, tcnt_0 and tcnt_1 perform an increment or decr ement operation. when tcnt_0 and gra_0 are compared and their contents match, the counter is decremented, and when tcnt_1 underflows, the counter is incremented. in gra_0, gra_1, and grb_1, compare match is carried out in the order of tcnt_0 tcnt_1 tcnt_1 tcnt_0 and pwm waveform is output, during one cycle of a up/down counter. in this mode, the initial setting will be tcnt_0 > tcnt_1. gra_0 grb_0 gra_1 grb_1 tcnt values tcnt_0 and gra_0 are compared and their contents match time h'0000 ftioa1 ftiob1 ftiob0 ftioc1 ftiod1 ftioc0 ftiod0 figure 13.31 example of complementary pwm mode operation (1)
section 13 timer z rev. 3.00 sep. 10, 2007 page 248 of 528 rej09b0216-0300 figure 13.32 (1) and (2) show examples of pwm waveform output with 0% duty and 100% duty in complementary pwm mode (for one phase). ? tpsc2 = tpsc1 = tpsc0 = 0 set grb_0 to h'0000 or a value equal to or more than gra_0. the waveform with a duty cycle of 0% and 100% can be output. when buffer operation is used together, the duty cycles can easily be changed, including the above settings, during operation. for details on buffer operation, refer to section 13.4.8, buffer operation. ? other than tpsc2 = tpsc1 = tpsc0 = 0 set grb_0 to satisfy the following expression: gra_0 + 1 < grb_0 < h'ffff. the waveform with a duty cycle of 0% and 100% can be output. for details on 0%- and 100%-duty cycle waveform output, see 3.c., outputting a wa veform with a duty cycle of 0% and 100% in section 13.4.7, complementary pwm mode.
section 13 timer z rev. 3.00 sep. 10, 2007 page 249 of 528 rej09b0216-0300 gra0 h'0000 ftiob0 ftiod0 gra0 (b) when duty is 100% 100% duty tcnt values tcnt values time time 0% duty (a) when duty is 0% grb0 h'0000 ftiob0 ftiod0 grb0 figure 13.32 (1) example of complementary pwm mode operation (tpsc2 = tpsc1 = tpsc0 = 0) (2)
section 13 timer z rev. 3.00 sep. 10, 2007 page 250 of 528 rej09b0216-0300 gra0 h'0000 ftiob0 ftiod0 gra0 (b) when duty is 100% 100% duty tcnt values tcnt values time time 0% duty (a) when duty is 0% grb0 h'0000 ftiob0 ftiod0 grb0 figure 13.32 (2) example of complementary pwm mode operation (tpsc2 = tpsc1 = tpsc0 0) (3)
section 13 timer z rev. 3.00 sep. 10, 2007 page 251 of 528 rej09b0216-0300 in complementary pwm mode, when the counter switches from up-counter to down-counter or vice versa, tcnt_0 and tcnt_1 overshoots or undershoots, respectively. in this case, the conditions to set the imfa flag in channel 0 and the udf flag in channel 1 differ from usual settings. also, the transfer conditions in buffer operation differ from usual settings. such timings are shown in figures 13.33 and 13.34. gr buffer transfer signal set to 1 flag is not set transferred to buffer not transferred to buffer n+1 gra_0 tcnt n n-1 n-1 n n imfa figure 13.33 timing of overshooting h'ffff h'0001 h'0001 h'0000 h'0000 gr udf tcnt buffer transfer signal set to 1 flag is not set transferred to buffer not transferred to buffer figure 13.34 timing of undershooting
section 13 timer z rev. 3.00 sep. 10, 2007 page 252 of 528 rej09b0216-0300 when the counter is incremented or decremented, the imfa flag of channel 0 is set to 1, and when the register is underflowed, the udf flag of channel 0 is set to 1. after buffer operation has been designated for br, br is transferred to gr when the counter is incremented by compare match a0 or when tcnt_1 is underflowed. if the or /2 clock is selected by tpsc2 to tpsc0 bits, the ovf flag is not set to 1 at the timing that the counter valu e changes from h' ffff to h' 0000. if the /4 or /8 clock is selected by tpsc2 to tpsc 0 bits, the ovf flag is set to 1. 3. setting gr value in complementary pwm mode: to set the general register (gr) or modify gr during operation in complementary pwm mode, refer to the following notes. a. initial value a. when other than tpsc2 = tpsc1 = tpsc0 = 0, the gra_0 value must be equal to h'fffc or less. when tpsc2 = tpsc1 = tpsc0 = 0, the gra_0 value can be set to h'ffff or less. b. h'0000 to t ? 1 (t: initial value of tcnt0) must not be set for the initial value. c. gra_0 ? (t ? 1) or more must not be set for the initial value. d. when using buffer operation, the same values must be set in the buffer registers and corresponding general registers. b. modifying the setting value a. writing to gr directly must be performed while the tcnt_1 and tcnt_0 values should satisfy the following expression: h'0000 tcnt_1 < previous gr value, and previous gr value < tcnt_0 gra_0. otherwise, a waveform is not output correctly. for details on outputting a waveform with a duty cycle of 0% and 100%, see c., outputting a waveform with a duty cycle of 0% and 100%. b. do not write the following values to gr directly. when writing the values, a waveform is not output correctly. h'0000 gr t ? 1 and gra_0 ? (t ? 1) gr < gra_0 when tpsc2 = tpsc1 = tpsc0 = 0 h'0000 < gr t ? 1 and gra_0 ? (t ? 1) gr < gra_0 + 1 when tpsc2 = tpsc1 = tpsc0 = 0 c. do not change settings of gra_0 during operation. c. outputting a waveform with a duty cycle of 0% and 100% a. buffer operation is not used and tpsc2 = tpsc1 = tpsc0 = 0 write h'0000 or a value equal to or more than the gra_0 value to gr directly at the timing shown below. ? to output a 0%-duty cycle waveform, write a value equal to or more than the gra_0 value while h'0000 tcnt_1 < previous gr value ? to output a 100%-duty cycle waveform, write h'0000 while previous gr value< tcnt_0 gra_0
section 13 timer z rev. 3.00 sep. 10, 2007 page 253 of 528 rej09b0216-0300 to change duty cycles while a waveform with a duty cycle of 0% or 100% is being output, make sure the following procedure. ? to change duty cycles while a 0%-duty cycle waveform is being output, write to gr while h'0000 tcnt_1 < previous gr value ? to change duty cycles while a 100%-duty cycle waveform is being output, write to gr while previous gr value< tcnt_0 gra_0 note that changing from a 0%-duty cycle waveform to a 100%-duty cycle waveform and vice versa is not possible. b. buffer operation is used and tpsc2 = tpsc1 = tpsc0 = 0 write h'0000 or a value equal to or more than the gra_0 value to the buffer register. ? to output a 0%-duty cycle waveform, write a value equal to or more than the gra_0 value to the buffer register ? to output a 100%-duty cycle waveform, write h'0000 to the buffer register for details on buffer operation, see section 13.4.8, buffer operation. c. buffer operation is not used and other than tpsc2 = tpsc1 = tpsc0 = 0 write a value which satisfies gra_0 + 1 < gr < h'ffff to gr directly at the timing shown below. ? to output a 0%-duty cycle waveform, write the value while h'0000 tcnt_1 < previous gr value ? to output a 100%-duty cycle waveform, write the value while previous gr value< tcnt_0 gra_0 to change duty cycles while a waveform with a duty cycle of 0% and 100% is being output, the following procedure must be followed. ? to change duty cycles while a 0%-duty cycle waveform is being output, write to gr while h'0000 tcnt_1 < previous gr value ? to change duty cycles while a 100%-duty cycle waveform is being output, write to gr while previous gr value< tcnt_0 gra_0 note that changing from a 0%-duty cycle waveform to a 100%-duty cycle waveform and vice versa is not possible. d. buffer operation is used and other than tpsc2 = tpsc1 = tpsc0 = 0 write a value which satisfies gra_0 + 1 < gr < h'ffff to the buffer register. a waveform with a duty cycle of 0% can be output. however, a waveform with a duty cycle of 100% cannot be output using the buffer operation. also, the buffer operation cannot be used to change duty cycles while a waveform with a duty cycle of 100% is being output. for details on buffer operation, see section 13.4.8, buffer operation.
section 13 timer z rev. 3.00 sep. 10, 2007 page 254 of 528 rej09b0216-0300 13.4.8 buffer operation buffer operation differs depending on whether gr has been designated for an input capture register or an output compare register, or in reset synchronous pwm mode or complementary pwm mode. table 13.8 shows the register combinations used in buffer operation. table 13.8 register combinat ions in buffer operation general register buffer register gra grc grb grd 1. when gr is an output compare register when a compare match occurs, the value in the buffer register of the corresponding channel is transferred to the general register. this operation is illustrated in figure 13.35. buffer register comparator tcnt general register compare match signal figure 13.35 compare match buffer operation 2. when gr is an input capture register when an input capture occurs, the value in tcnt is transferred to the general register and the value previously stored in the general register is transferred to the buffer register. this operation is illustrated in figure 13.36.
section 13 timer z rev. 3.00 sep. 10, 2007 page 255 of 528 rej09b0216-0300 tcnt buffer register general register input capture signal figure 13.36 input capture buffer operation 3. complementary pwm mode when the counter switches from counting up to counting down or vice versa, the value of the buffer register is transferred to the general regi ster. here, the value of the buffer register is transferred to the general register in the following timing: a. when tcnt_0 and gra_0 are compared and their contents match b. when tcnt_1 underflows 4. reset synchronous pwm mode the value of the buffer register is transferred from compare match a0 to the general register. 5. example of buffer operation setting procedure figure 13.37 shows an example of the buffer operation setting procedure. [1] designate gr as an input capture register or output compare register by means of tior. [2] designate gr for buffer operation with bits bfd1, bfc1, bfd0, or bfc0 in tmdr. [3] set the str bit in tstr to 1 to start the count operation of tcnt. [1] [2] [3] select gr function set buffer operation start count operation buffer operation figure 13.37 example of buffer operation setting procedure
section 13 timer z rev. 3.00 sep. 10, 2007 page 256 of 528 rej09b0216-0300 6. examples of buffer operation figure 13.38 shows an operation example in which gra has been designated as an output compare register, and buffer operation has been designated for gra and grc. this is an example of tcnt operating as a periodic counter cleared by compare match b. pins ftioa and ftiob are set for toggle output by compare match a and b. as buffer operation has been set, when compare match a occurs, the ftioa pin performs toggle outputs and the value in buffer register is simultaneously transferred to the general register. this operation is repeated each time that compar e match a occurs. the timing to transfer data is shown in figure 13.39. grb tcnt value counter is cleared by gbr compare match time compare match a h'0250 h'0200 h'0100 h'0000 ftiob ftioa h'0200 h'0250 h'0200 h'0200 h'0100 h'0200 grc h'0100 gra figure 13.38 example of buffer operation (1) (buffer operation for ou tput compare register)
section 13 timer z rev. 3.00 sep. 10, 2007 page 257 of 528 rej09b0216-0300 gra n n tcnt compare match signal buffer transfer signal n n+1 grc n figure 13.39 example of compare match timing for buffer operation
section 13 timer z rev. 3.00 sep. 10, 2007 page 258 of 528 rej09b0216-0300 figure 13.40 shows an operation example in which gra has been designated as an input capture register, and buffer operation has been designated for gra and grc. counter clearing by input capture b has been set for tcnt, and falling edges have been selected as the fiocb pin input capture input edge. and both ri sing and falling edges ha ve been selected as the fioca pin input capture input edge. as buffer operation has been set, when the tcnt value is stored in gra upon the occurrence of input capture a, the value previously stored in gra is simultaneously transferred to grc. the transfer timing is shown in figure 13.41. h'0180 h'0160 h'0005 h'0000 ftiob ftioa h'0160 h'0005 h'0005 gra h'0160 grc h'0180 grb tcnt value counter is cleared by the input capture b time input capture a figure 13.40 example of buffer operation (2) (buffer operation for input capture register)
section 13 timer z rev. 3.00 sep. 10, 2007 page 259 of 528 rej09b0216-0300 tcnt ftio pin input capture signal nnn+1 n+1 gra m n n n grc m m n m figure 13.41 input capture timing of buffer operation
section 13 timer z rev. 3.00 sep. 10, 2007 page 260 of 528 rej09b0216-0300 figures 13.42 and 13.43 show the operation exampl es when buffer operation has been designated for grb_0 and grd_0 in complementary pw m mode. these are examples when a pwm waveform of 0% duty is created by using the buffer operation and performing grd_0 gra_0. data is transferred from grd_0 to grb_0 accord ing to the settings of cmd_0 and cmd_1 when tcnt_0 and gra_0 are compared and their contents match or when tcnt_1 underflows. however, when grd_0 gra_0, data is transferred from grd_0 to grb_0 when tcnt_1 underflows regardless of the setting of cmd_0 an d cmd_1. when grd_0 = h'0000, data is transferred from grd_0 to grb_0 when tcnt_0 and gra_0 are compared and their contents match regardless of the settings of cmd_0 and cmd_1. gra_0 h'0000 h'0999 ftiob0 ftiod0 tcnt_0 tcnt values time grb_0 (when restored, data will be transferred to the saved location regardless of the cmd1 and cmd0 values) tcnt_1 h'0999 h'0999 h'0999 h'0999 h'1fff h'0999 grd_0 h'1fff grb_0 figure 13.42 buffer operation (3) (buffer operation in complementary pwm mode cmd1 = cmd0 = 1)
section 13 timer z rev. 3.00 sep. 10, 2007 page 261 of 528 rej09b0216-0300 gra_0 h'0000 h'0999 ftioc0 ftiod0 tcnt values grb_0 (when restored, data will be transferred to the saved location regardless of the cmd1 and cmd0 values) time tcnt_0 tcnt_1 grb_0 h'0999 h'0999 h'0999 h'0000 h'0999 h'0000 grd_0 grb_0 figure 13.43 buffer operation (4) (buffer operation in complementary pwm mode cmd1 = cmd0 = 1)
section 13 timer z rev. 3.00 sep. 10, 2007 page 262 of 528 rej09b0216-0300 13.4.9 timer z output timing the outputs of channels 0 and 1 can be disabled or inverted by the settings of toer and tocr and the external level. 1. output disable/enable timing of timer z by toer: setting the master enable bit in toer to 1 disables the output of timer z. by setting the pcr and pdr of the corresponding i/o port beforehand, any value can be output. figure 13.44 shows the timing to enable or disable the output of timer z by toer. t 1 t 2 toer address bus toer address timer z output pin i/o port timer output timer z output i/o port n h'ff figure 13.44 example of output disable timing of timer z by writing to toer
section 13 timer z rev. 3.00 sep. 10, 2007 page 263 of 528 rej09b0216-0300 2. output disable timing of timer z by external trigger: when p54/ wkp4 is set as a wkp4 input pin, and low level is input to wkp4 , the master enable bit in toer is set to 1 and the output of timer z will be disabled. wkp4 toer timer z output pin timer z output i/o port timer z output i/o port n h'ff figure 13.45 example of output disable timing of timer z by external trigger
section 13 timer z rev. 3.00 sep. 10, 2007 page 264 of 528 rej09b0216-0300 3. output inverse timing by tfcr: the output level can be inverted by inverting the ols1 and ols0 bits in tfcr in reset synchronous pwm mode or complementary pwm mode. figure 13.46 shows the timing. t 1 t 2 tfcr inverted timer z output pin address bus toer address figure 13.46 example of output inverse timing of timer z by writing to tfcr 4. output inverse timing by pocr: the output level can be inverted by inverting the pold, polc, and polb bits in pocr in pwm mode. figure 13.47 shows the timing. t 1 t 2 tfcr address bus pocr address timer z output pin inverted figure 13.47 example of output inverse timing of timer z by writing to pocr
section 13 timer z rev. 3.00 sep. 10, 2007 page 265 of 528 rej09b0216-0300 13.5 interrupts there are three kinds of timer z interrupt sources; input capture/compare match, overflow, and underflow. an interrupt is requested when the corresponding interrupt request flag is set to 1 while the corresponding interrupt enable bit is set to 1. 13.5.1 status flag set timing 1. imf flag set timing: the imf flag is set to 1 by the compare match signal that is generated when the gr matches with the tcnt. the compare match signal is generated at the last state of matching (timing to update the counter value when the gr and tcnt match). therefore, when the tcnt and gr matches, the compare match signal will not be generated until the tcnt input clock is generated. figure 13.48 shows the timing to set the imf flag. imf itmz tcnt tcnt input clock compare match signal n n+1 gr n figure 13.48 imf flag set timi ng when compare match occurs
section 13 timer z rev. 3.00 sep. 10, 2007 page 266 of 528 rej09b0216-0300 2. imf flag set timing at input capture: when an input capture signal is generated, the imf flag is set to 1 and the value of tcnt is simultaneously transferred to corresponding gr. figure 13.49 shows the timing. imf input capture signal tcnt n gr n itmz figure 13.49 imf flag set timing at input capture 3. overflow flag (ovf) set timing: the overflow flag is set to 1 when the tcnt overflows. figure 13.50 shows the timing. ovf tcnt overflow signal h'0000 h'ffff itmz figure 13.50 ovf flag set timing
section 13 timer z rev. 3.00 sep. 10, 2007 page 267 of 528 rej09b0216-0300 13.5.2 status flag clearing timing the status flag can be cleared by writing 0 after reading 1 from the cpu. figure 13.51 shows the timing in this case. address tsr address wtsr (internal write signal) imf, ovf itmz figure 13.51 status flag clearing timing
section 13 timer z rev. 3.00 sep. 10, 2007 page 268 of 528 rej09b0216-0300 13.6 usage notes 1. contention between tcnt write and clear operations: if a counter clear signal is generated in the t 2 state of a tcnt write cycle, tcnt cleari ng has priority and the tcnt write is not performed. figure 13.52 shows the timing in this case. t 1 t 2 tcnt tcnt write cycle tcnt address wtcnt (internal write signal) clearing has priority. counter clear signal n h'0000 figure 13.52 contention between tcnt write and clear operations 2. contention between tcnt write and increment operations: if increment is done in t 2 state of a tcnt write cycle, tcnt writing has priority . figure 13.53 shows the timing in this case.
section 13 timer z rev. 3.00 sep. 10, 2007 page 269 of 528 rej09b0216-0300 t 1 t 2 tcnt tcnt write cycle tcnt address wtcnt (internal write signal) tcnt input clock tcnt write data n m figure 13.53 contenti on between tcnt write and increment operations 3. contention between gr write and compare ma tch: if a compare match occurs in the t 2 state of a gr write cycle, gr write has priority and the compare match signal is disabled. figure 13.54 shows the timing in this case. t 1 t 2 gr n m tcnt gr write cycle gr address wgr (internal write signal) gr write data compare match signal disabled n n+1 figure 13.54 contention betw een gr write and compare match
section 13 timer z rev. 3.00 sep. 10, 2007 page 270 of 528 rej09b0216-0300 4. contention between tcnt write and overflow/underflow: if overflow/underflow occurs in the t 2 state of a tcnt write cycle, tcnt write has priority without an increment operation. at this time, the ovf flag is set to 1. figure 13.55 shows the timing in this case. t 1 t 2 tcnt h'ffff m ovf tcnt address wtcnt (internal write signal) tcnt input clock overflow signal tcnt write data tcnt write cycle figure 13.55 contention be tween tcnt write and overflow
section 13 timer z rev. 3.00 sep. 10, 2007 page 271 of 528 rej09b0216-0300 5. contention between gr read and input capture: if an input capture signal is generated in the t 1 state of a gr read cycle, the data that is read will be transferred before input capture transfer. figure 13.56 shows the timing in this case. t 1 t 2 gr gr read cycle gr address internal read signal input capture signal internal data bus x x m figure 13.56 contention betw een gr read and input capture
section 13 timer z rev. 3.00 sep. 10, 2007 page 272 of 528 rej09b0216-0300 6. contention between count clearing and increment operations by input capture: if an input capture and increment signals are simultaneously generated, count clearing by the input capture operation has priority without an increment operation. the tcnt contents before clearing counter are transferred to gr. fi gure 13.57 shows the timing in this case. tcnt input capture signal counter clear signal tcnt input clock clearing has priority. n h'0000 gr n figure 13.57 contention between count clearing and increment operations by input capture
section 13 timer z rev. 3.00 sep. 10, 2007 page 273 of 528 rej09b0216-0300 7. contention between gr write and input capture: if an input capture signal is generated in the t 2 state of a gr write cycle, the input capture operation has priority and the write to gr is not performed. figure 13.58 shows the timing in this case. t 1 t 2 tcnt n gr write cycle gr address input capture signal wgr (internal write signal) address bus gr write data gr m figure 13.58 contention betw een gr write and input capture 8. notes on setting reset synchronous pwm mode/complementary pwm mode: when bits cmd1 and cmd0 in tfcr are set, note the following: a. write bits cmd1 and cmd0 while tcnt_1 and tcnt_0 are halted. b. changing the settings of reset synchronous pwm mode to complementary pwm mode or vice versa is disabled. set reset synchronous pwm mode or complementary pwm mode after the normal operation (bits cmd1 and cmd0 are cleared to 0) has been set.
section 13 timer z rev. 3.00 sep. 10, 2007 page 274 of 528 rej09b0216-0300 9. note on writing to the toa0 to tod0 bits and the toa1 to tod1 bits in tocr: the toa0 to tod0 bits and the toa1 to tod1 bits in tocr decide the value of the ftio pin, which is output until the first compare match occurs. once a compare match occurs and this compare match changes the values of ftioa0 to ftiod0 and ftioa1 to ftiod1 output, the values of the ftioa0 to ftiod0 and ftioa1 to ftiod1 pin output and the values read from the toa0 to tod0 and toa1 to tod1 bits may differ. moreover, when the writing to tocr and the generation of the compare match a0 to d0 and a1 to d1 occur at the same timing, the writing to tocr has the priority. thus, output change due to the compare match is not reflected to the ftioa0 to fti od0 and ftioa1 to ftiod1 pins. therefore, when bit manipulation instruction is used to write to tocr, the values of the ftioa0 to ftiod0 and ftioa1 to ftiod1 pin output may result in an unexpected result. when tocr is to be written to while compare match is ope rating, stop the counter once before accessing to tocr, read the port 6 state to reflect the va lues of ftioa0 to ftiod0 and ftioa1 to ftiod1 output, to toa0 to tod0 and toa1 to tod1, and then restart the counter. figure 13.59 shows an example when the compare match and the bit manipulation instruction to tocr occur at the same timing. compare match signal b0 ftiob0 pin tocr write signal set value bit tocr 000 00110 765 43210 tod1 toc1 tob1 toa1 tod0 toc0 tob0 toa0 expected output remains high because the 1 writing to tob has priority tocr has been set to h'06. compare match b0 and compare match c0 are used. the ftiob0 pin is in the 1 output state, and is set to the toggle output or the 0 output by compare match b0. when bclr#2, @tocr is executed to clear the toc0 bit (the ftioc0 signal is low) and compare match b0 occurs at the same timing as shown below, the h'02 writing to tocr has priority and compare match b0 does not drive the ftiob0 signal low; the ftiob0 signal remains high. bclr#2, @tocr (1) tocr read operation: read h'06 (2) modify operation: modify h'06 to h'02 (3) write operation to tocr: write h'02 figure 13.59 when compare match and bit manipulation instruction to tocr occur at the same timing
section 14 watchdog timer wdt0110a_000020030700 rev. 3.00 sep. 10, 2007 page 275 of 528 rej09b0216-0300 section 14 watchdog timer the watchdog timer is an 8-bit timer that can generate an internal reset signal for this lsi if a system crash prevents the cpu from writing to the timer counter, thus allowing it to overflow. the block diagram of the watchdog timer is shown in figure 14.1. internal reset signal pss tcwd tmwd tcsrwd internal data bus [legend] tcsrwd: timer control/status register wd tcwd: timer counter wd pss: prescaler s tmwd: timer mode register wd wdt dedicated internal oscillator clk figure 14.1 block diagram of watchdog timer 14.1 features ? selectable from nine counter input clocks. eight clock sources ( /64, /128, /256, /512, /1024, /2048, /4096, and /8192) or the wdt dedicated internal oscillator can be select ed as the timer-counter clock. when the wdt dedicated internal oscillator is selected, it can operate as the watchdog timer in any operating mode. ? reset signal generated on counter overflow an overflow period of 1 to 256 times the selected clock can be set. ? the watchdog timer is enabled in the initial state. it starts operating after the reset state is canceled.
section 14 watchdog timer rev. 3.00 sep. 10, 2007 page 276 of 528 rej09b0216-0300 14.2 register descriptions the watchdog timer has the following registers. ? timer control/status register wd (tcsrwd) ? timer counter wd (tcwd) ? timer mode register wd (tmwd) 14.2.1 timer control/statu s register wd (tcsrwd) tcsrwd performs the tcsrwd and tcwd write control. tcsrwd also controls the watchdog timer operation and indicates the operatin g state. tcsrwd must be rewritten by using the mov instruction. the bit manipulation instruction cannot be used to change the setting value. bit bit name initial value r/w description 7 b6wi 1 r/w bit 6 write inhibit the tcwe bit can be written only when the write value of the b6wi bit is 0. this bit is always read as 1. 6 tcwe 0 r/w timer counter wd write enable tcwd can be written when the tcwe bit is set to 1. when writing data to this bit, the value for bit 7 must be 0. 5 b4wi 1 r/w bit 4 write inhibit the tcsrwe bit can be written only when the write value of the b4wi bit is 0. this bit is always read as 1. 4 tcsrwe 0 r/w timer control/status register wd write enable the wdon and wrst bits can be written when the tcsrwe bit is set to 1. when writing data to this bit, the value for bit 5 must be 0. 3 b2wi 1 r/w bit 2 write inhibit this bit can be written to the wdon bit only when the write value of the b2wi bit is 0. this bit is always read as 1.
section 14 watchdog timer rev. 3.00 sep. 10, 2007 page 277 of 528 rej09b0216-0300 bit bit name initial value r/w description 2 wdon 1 r/w watchdog timer on tcwd starts counting up when the wdon bit is set to 1 and halts when the wdon bit is cleared to 0. the watchdog timer is enabled in the initial state. when the watchdog timer is not used, clear the wdon bit to 0. [setting conditions] ? reset ? when 1 is written to the wdon bit and 0 is written to the b2wi bit while the tcsrwe bit = 1 [clearing condition] ? when 0 is written to the wdon bit and 0 is written to the b2wi bit while the tcsrwe bit = 1 1 b0wi 1 r/w bit 0 write inhibit this bit can be written to the wrst bit only when the write value of the b0wi bit is 0. this bit is always read as 1. 0 wrst 0 r/w watchdog timer reset [setting condition] ? when tcwd overflows and an internal reset signal is generated [clearing conditions] ? reset by the res pin ? when 0 is written to the wrst bit and 0 is written to the b0wi bit while the tcsrwe bit = 1
section 14 watchdog timer rev. 3.00 sep. 10, 2007 page 278 of 528 rej09b0216-0300 14.2.2 timer counter wd (tcwd) tcwd is an 8-bit readable/writable up-counter. when tcwd overflows from h'ff to h'00, the internal reset signal is generated and the wrst bit in tcsrwd is set to 1. tcwd is initialized to h'00. 14.2.3 timer mode register wd (tmwd) tmwd selects the input clock. bit bit name initial value r/w description 7 to 4 ? all 1 ? reserved these bits are always read as 1. 3 2 1 0 cks3 cks2 cks1 cks0 1 1 1 1 r/w r/w r/w r/w clock select 3 to 0 select the clock to be input to tcwd. 1000: internal clock: counts on /64 1001: internal clock: counts on /128 1010: internal clock: counts on /256 1011: internal clock: counts on /512 1100: internal clock: counts on /1024 1101: internal clock: counts on /2048 1110: internal clock: counts on /4096 1111: internal clock: counts on 8192 0xxx: wdt dedicated internal oscillator for the overflow periods of the wdt dedicated internal oscillator, see section 22, electrical characteristics. [legend] x: don't care.
section 14 watchdog timer rev. 3.00 sep. 10, 2007 page 279 of 528 rej09b0216-0300 14.3 operation the watchdog timer is provided with an 8-bit counter. after the reset state is released, tcwd starts counting up. when the tcwd count value overflows h'ff, an internal reset signal is generated. the internal reset signal is output for a period of 256 osc clock cycles. as tcwd is a writable counter, it starts counting from the value set in tcwd. an overflow period in the range of 1 to 256 input clock cycles can therefore be set, according to the tcwd set value. when the watchdog timer is not used, stop tcwd counting by writing 0 to b2wi and wdon simultaneously while the tcsrwe bit in tcsrwd is set to 1. (to stop the watchdog timer, two write accesses to tcsrwd are required.) figure 14.2 shows an example of watchdog timer operation. example: with 30-ms overflow period when = 4 mhz 4 10 6 30 10 ?3 = 14.6 8192 tcwd overflow h'ff h'00 internal reset signal h'f1 tcwd count value h'f1 written to tcwd h'f1 written to tcwd reset generated 256 osc clock cycles therefore, 256 ? 15 = 241 (h'f1) is set in tcw. figure 14.2 watchdog timer operation example
section 14 watchdog timer rev. 3.00 sep. 10, 2007 page 280 of 528 rej09b0216-0300
section 15 14-bit pwm pwm1400a_000120030300 rev. 3.00 sep. 10, 2007 page 281 of 528 rej09b0216-0300 section 15 14-bit pwm the 14-bit pwm is a pulse division type pwm that can be used for electronic tuner control, etc. figure 15.1 shows a block diagram of the 14-bit pwm. 15.1 features ? choice of two conversion periods a conversion period of 32768/ with a minimum modulation width of 2/ , or a conversion period of 16384/ with a minimum modulation width of 1/ , can be selected. ? pulse division method for less ripple pwcr: pwm control register [legend] internal data bus pwdrl: pwm data register l pwdru: pwm data register u pwm: pwm output pin pwcr pwdrl pwdru pwm pwm waveform generator /4 /2 figure 15.1 block diagram of 14-bit pwm
section 15 14-bit pwm rev. 3.00 sep. 10, 2007 page 282 of 528 rej09b0216-0300 15.2 input/output pin table 15.1 shows the 14-bit pwm pin configuration. table 15.1 pin configuration name abbreviation i/o function 14-bit pwm square-wave output pwm output 14-bit pwm square-wave output pin
section 15 14-bit pwm rev. 3.00 sep. 10, 2007 page 283 of 528 rej09b0216-0300 15.3 register descriptions the 14-bit pwm has the following registers. ? pwm control register (pwcr) ? pwm data register u (pwdru) ? pwm data register l (pwdrl) 15.3.1 pwm control register (pwcr) pwcr selects the conversion period. bit bit name initial value r/w description 7 to 1 ? all 1 ? reserved these bits are always read as 1, and cannot be modified. 0 pwcr0 0 r/w clock select 0: the input clock is /2 (t = 2/ ) ? the conversion period is 16384/ , with a minimum modulation width of 1/ 1: the input clock is /4 (t = 4/ ) ? the conversion period is 32768/ , with a minimum modulation width of 2/ [legend] t : period of pwm clock input 15.3.2 pwm data registers u and l (pwdru, pwdrl) pwdru and pwdrl indicate high level width in one pwm waveform cycle. pwdru and pwdrl are 14-bit write-only registers, with the upper 6 bits assigned to pwdru and the lower 8 bits to pwdrl. when read, all b its are always read as 1. both pwdru and pwdrl are accessible only in bytes. note that the operation is not guaranteed if word access is performed. when 14-bit data is written in pwdru and pwdrl, the contents are latched in the pwm waveform generator and th e pwm waveform generation data is updated. when writing the 14-bit data, the orde r is as follows: pwdrl to pwdru. pwdru and pwdrl are initialized to h'c000.
section 15 14-bit pwm rev. 3.00 sep. 10, 2007 page 284 of 528 rej09b0216-0300 15.4 operation when using the 14-bit pwm, set the registers in this sequence: 1. set the pwm bit in the port mode register 1 (pmr1) to set the p11/pwm pin to function as a pwm output pin. 2. set the pwcr0 bit in pwcr to select a conversion period of either. 3. set the output waveform data in pwdru and pwdrl. be sure to write byte data first to pwdrl and then to pwdru. when the data is written in pwdru, the contents of these registers are latched in the pwm waveform generator, and the pwm waveform generation data is updated in synchronization with internal signals. one conversion period consists of 64 pulses, as shown in figure 15.2. the total high-level width during this period (t h ) corresponds to the data in pwdru and pwdrl. this relation can be expressed as follows: t h = (data value in pwdru and pwdrl + 64) t /2 where t is the period of pwm clock input: 2/ (bit pwcr0 = 0) or 4/ (bit pwcr0 = 1). if the data value in pwdru and pwdrl is from h'ffc0 to h'ffff, the pwm output stays high. when the data value is h'c000, t h is calculated as follows: t h = 64 t /2 = 32 t t h64 t h63 t h3 t h2 t h1 t h = t h1 + t h2 + t h3 + ... + t h64 t f1 = t f2 = t f3 = ... = t f64 t f1 t f2 t f63 t f64 conversion period figure 15.2 waveform output by 14-bit pwm
section 16 serial communication interface 3 (sci3) sci0011a_000020020200 rev. 3.00 sep. 10, 2007 page 285 of 528 rej09b0216-0300 section 16 serial communication interface 3 (sci3) this lsi includes a serial comm unication interface 3 (sci3), which has independent two channels. the sci3 can handle both asynchronous and clock synchronous serial communication. in asynchronous mode, serial data communication can be carried out using standard asynchronous communication chips such as a universal asynchronous receiver/transmitter (uart) or an asynchronous communication interface adapter (acia). a function is also provided for serial communication between processors (multiprocessor communication function). table 16.1 shows the sci3 channel configuration and figure 16.1 shows a block diagram of the sci3. since pin functions are identical for each of the two channels (sci3 and sci3_2), separate explanations are not given in this section. 16.1 features ? choice of asynchronous or clock synchronous serial communication mode ? full-duplex communication capability the transmitter and receiver are mutually indepe ndent, enabling transmission and reception to be executed simultaneously. double-buffering is used in both the tran smitter and the receiver, enabling continuous transmission and continuous reception of serial data. ? on-chip baud rate generator allows any bit rate to be selected ? external clock or on-chip baud rate generator can be selected as a transfer clock source. ? six interrupt sources transmit-end, transmit-data-empty , receive-data-full, overrun error, framing error, and parity error. asynchronous mode ? data length: 7 or 8 bits ? stop bit length: 1 or 2 bits ? parity: even, odd, or none ? receive error detection: parity , overrun, and framing errors ? break detection: break can be de tected by reading the rxd pin le vel directly in the case of a framing error
section 16 serial communication interface 3 (sci3) rev. 3.00 sep. 10, 2007 page 286 of 528 rej09b0216-0300 clock synchronous mode ? data length: 8 bits ? receive error detecti on: overrun errors table 16.1 channel configuration channel abbreviation pin re gister register address smr h'ffa8 brr h'ffa9 scr3 h'ffaa tdr h'ffab ssr h'ffac rdr h'ffad rsr ? channel 1 sci3 * sck3 rxd txd tsr ? smr_2 h'f740 brr_2 h'f741 scr3_2 h'f742 tdr_2 h'f743 ssr_2 h'f744 rdr_2 h'f745 rsr_2 ? channel 2 sci3_2 sck3_2 rxd_2 txd_2 tsr_2 ? note: * the channel 1 of the sci3 is used in on-board programming mode by boot mode.
section 16 serial communication interface 3 (sci3) rev. 3.00 sep. 10, 2007 page 287 of 528 rej09b0216-0300 clock txd rxd sck 3 tsr rsr transmit/receive control circuit internal data bus [legend] rsr: rdr: tsr: tdr: smr: scr3: ssr: brr: brc: receive shift register receive data register transmit shift register transmit data register serial mode register serial control register 3 serial status register bit rate register bit rate counter interrupt request (tei, txi, rxi, eri) internal clock ( /64, /16, /4, ) external clock brc baud rate generator brr smr scr3 ssr tdr rdr figure 16.1 block diagram of sci3
section 16 serial communication interface 3 (sci3) rev. 3.00 sep. 10, 2007 page 288 of 528 rej09b0216-0300 16.2 input/output pins table 16.2 shows the sci3 pin configuration. table 16.2 pin configuration pin name abbreviation i/o function sci3 clock sck3 i/o sci3 clock input/output sci3 receive data input rxd input sci3 receive data input sci3 transmit data output txd output sci3 transmit data output
section 16 serial communication interface 3 (sci3) rev. 3.00 sep. 10, 2007 page 289 of 528 rej09b0216-0300 16.3 register descriptions the sci3 has the following registers for each channel. ? receive shift register (rsr) ? receive data register (rdr) ? transmit shift register (tsr) ? transmit data register (tdr) ? serial mode register (smr) ? serial control register 3 (scr3) ? serial status register (ssr) ? bit rate register (brr) 16.3.1 receive shift register (rsr) rsr is a shift register that is used to receive se rial data input from the rxd pin and convert it into parallel data. when one frame of data has been r eceived, it is transferred to rdr automatically. rsr cannot be directly accessed by the cpu. 16.3.2 receive data register (rdr) rdr is an 8-bit register that stores received data . when the sci3 has received one frame of serial data, it transfers the received serial data from rs r to rdr, where it is st ored. after this, rsr is receive-enabled. as rsr and rdr function as a double buffer in this way, continuous receive operations are possible. after confirming that the rdrf bit in ssr is set to 1, read rdr only once. rdr cannot be written to by the cpu. rdr is initialized to h'00. 16.3.3 transmit shift register (tsr) tsr is a shift register that transmits serial data. to perform serial data transmission, the sci3 first transfers transmit data from tdr to tsr automatically, then sends the data that starts from the lsb to the txd pin . tsr cannot be directly accessed by the cpu.
section 16 serial communication interface 3 (sci3) rev. 3.00 sep. 10, 2007 page 290 of 528 rej09b0216-0300 16.3.4 transmit data register (tdr) tdr is an 8-bit register that stores data for transmission. when the sc i3 detects that tsr is empty, it transfers the transmit data written in tdr to tsr and starts transmission. the double- buffered structure of tdr and tsr enables continuous serial transmission. if the next transmit data has already been written to tdr during transmission of one-frame data, the sci3 transfers the written data to tsr to continue transmission. to achieve reliable serial transmission, write transmit data to tdr only once after confirming that the tdre bit in ssr is set to 1. tdr is initialized to h'ff. 16.3.5 serial mode register (smr) smr is used to set the sci3?s serial transfer format and select the baud rate generator clock source. bit bit name initial value r/w description 7 com 0 r/w communication mode 0: asynchronous mode 1: clock synchronous mode 6 chr 0 r/w character length (enabled only in asynchronous mode) 0: selects 8 bits as the data length. 1: selects 7 bits as the data length. 5 pe 0 r/w parity enable (enabled only in asynchronous mode) when this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. 4 pm 0 r/w parity mode (enabled only when the pe bit is 1 in asynchronous mode) 0: selects even parity. 1: selects odd parity.
section 16 serial communication interface 3 (sci3) rev. 3.00 sep. 10, 2007 page 291 of 528 rej09b0216-0300 bit bit name initial value r/w description 3 stop 0 r/w stop bit length (enabled only in asynchronous mode) selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits for reception, only the first stop bit is checked, regardless of the value in the bit. if the second stop bit is 0, it is treated as the start bit of the next transmit character. 2 mp 0 r/w multiprocessor mode when this bit is set to 1, the multiprocessor communication function is enabled. the pe bit and pm bit settings are invalid in multiprocessor mode. in clock synchronous mode, clear this bit to 0. 1 0 cks1 cks0 0 0 r/w r/w clock select 0 and 1 these bits select the clock source for the baud rate generator. 00: clock (n = 0) 01: /4 clock (n = 1) 10: /16 clock (n = 2) 11: /64 clock (n = 3) for the relationship between the bit rate register setting and the baud rate, see section 16.3.8, bit rate register (brr). n is the decimal representation of the value of n in brr (see section 16.3.8, bit rate register (brr)).
section 16 serial communication interface 3 (sci3) rev. 3.00 sep. 10, 2007 page 292 of 528 rej09b0216-0300 16.3.6 serial control register 3 (scr3) scr3 is a register that enables or disables sci3 transfer operations and interrupt requests, and is also used to select the transfer clock source. for details on interrupt requests, refer to section 16.7, interrupts. bit bit name initial value r/w description 7 tie 0 r/w transmit interrupt enable when this bit is set to 1, the txi interrupt request is enabled. 6 rie 0 r/w receive interrupt enable when this bit is set to 1, rxi and eri interrupt requests are enabled. 5 te 0 r/w transmit enable when this bit s set to 1, transmission is enabled. 4 re 0 r/w receive enable when this bit is set to 1, reception is enabled. 3 mpie 0 r/w multiprocessor interrupt enable (enabled only when the mp bit in smr is 1 in asynchronous mode) when this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the rdrf, fer, and oer status flags in ssr is disabled. on receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed. for details, refer to section 16.6, multiprocessor communication function. 2 teie 0 r/w transmit end interrupt enable when this bit is set to 1, tei interrupt request is enabled.
section 16 serial communication interface 3 (sci3) rev. 3.00 sep. 10, 2007 page 293 of 528 rej09b0216-0300 bit bit name initial value r/w description 1 0 cke1 cke0 0 0 r/w r/w clock enable 0 and 1 selects the clock source. ? asynchronous mode 00: on-chip baud rate generator 01: on-chip baud rate generator outputs a clock of the same frequency as the bit rate from the sck3 pin. 10: external clock inputs a clock with a frequency 16 times the bit rate from the sck3 pin. 11:reserved ? clock synchronous mode 00: on-chip clock (sck3 pin functions as clock output) 01: reserved 10: external clock (sck3 pin functions as clock input) 11: reserved
section 16 serial communication interface 3 (sci3) rev. 3.00 sep. 10, 2007 page 294 of 528 rej09b0216-0300 16.3.7 serial status register (ssr) ssr is a register containing status flags of the sci3 and multiprocessor bits for transfer. 1 cannot be written to flags tdre, rdrf, oer, per, and fer; they can only be cleared. bit bit name initial value r/w description 7 tdre 1 r/w transmit data register empty indicates whether tdr contains transmit data. [setting conditions] ? when the te bit in scr3 is 0 ? when data is transferred from tdr to tsr [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 ? when the transmit data is written to tdr 6 rdrf 0 r/w receive data register full indicates that the received data is stored in rdr. [setting condition] ? when serial reception ends normally and receive data is transferred from rsr to rdr [clearing conditions] ? when 0 is written to rdrf after reading rdrf = 1 ? when data is read from rdr 5 oer 0 r/w overrun error [setting condition] ? when an overrun error occurs in reception [clearing condition] ? when 0 is written to oer after reading oer = 1 4 fer 0 r/w framing error [setting condition] ? when a framing error occurs in reception [clearing condition] ? when 0 is written to fer after reading fer = 1
section 16 serial communication interface 3 (sci3) rev. 3.00 sep. 10, 2007 page 295 of 528 rej09b0216-0300 bit bit name initial value r/w description 3 per 0 r/w parity error [setting condition] ? when a parity error is detected during reception [clearing condition] ? when 0 is written to per after reading per = 1 2 tend 1 r transmit end [setting conditions] ? when the te bit in scr3 is 0 ? when tdre = 1 at transmission of the last bit of a 1- frame serial transmit character [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 ? when the transmit data is written to tdr 1 mpbr 0 r multiprocessor bit receive mpbr stores the multiprocessor bit in the receive character data. when the re bit in scr3 is cleared to 0, its state is retained. 0 mpbt 0 r/w multiprocessor bit transfer mpbt stores the multiprocessor bit to be added to the transmit character data.
section 16 serial communication interface 3 (sci3) rev. 3.00 sep. 10, 2007 page 296 of 528 rej09b0216-0300 16.3.8 bit rate register (brr) brr is an 8-bit register that adjusts the bit rate. the initial value of brr is h'ff. table 16.3 shows the relationship between the n setting in brr and the n setting in bits cks1 and cks0 of smr in asynchronous mode. table 16.4 shows th e maximum bit rate for each frequency in asynchronous mode. the values shown in both tables 16.3 and 16.4 are values in active (high- speed) mode. table 16.5 shows the relationship between the n setting in brr and the n setting in bits cks1 and cks0 of smr in clock synchronous mode. the values shown in table 16.5 are values in active (high-speed) mode. the n setting in brr and error for other operating frequencies and bit rates can be obtained by the following formulas: [asynchronous mode] n = 64 2 2n?1 b 10 6 ? 1 error (%) = ? 1 100 ? ? ? ? ? ? 10 6 (n + 1) b 64 2 2n?1 [clock synchronous mode] n = 8 2 2n?1 b 10 6 ? 1 [legend] b: bit rate (bit/s) n: brr setting for baud rate generator (0 n 255) : operating frequency (mhz) n: csk1 and csk0 settings in smr (0 n 3)
section 16 serial communication interface 3 (sci3) rev. 3.00 sep. 10, 2007 page 297 of 528 rej09b0216-0300 table 16.3 examples of brr settings for various bit rates (asynchronous mode) (1) operating frequency (mhz) 2 2.097152 2.4576 3 bit rate (bits/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 1 141 0.03 1 148 ?0.04 1 174 ?0.26 1 212 0.03 150 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.16 300 0 207 0.16 0 217 0.21 0 255 0.00 1 77 0.16 600 0 103 0.16 0 108 0.21 0 127 0.00 0 155 0.16 1200 0 51 0.16 0 54 ?0.70 0 63 0.00 0 77 0.16 2400 0 25 0.16 0 26 1.14 0 31 0.00 0 38 0.16 4800 0 12 0.16 0 13 ?2.48 0 15 0.00 0 19 ?2.34 9600 0 6 ?6.99 0 6 ?2.48 0 7 0.00 0 9 ?2.34 19200 0 2 8.51 0 2 13.78 0 3 0.00 0 4 ?2.34 31250 0 1 0.00 0 1 4.86 0 1 22.88 0 2 0.00 38400 0 1 ?18.62 0 1 ?14.67 0 1 0.00 ? ? ? operating frequency (mhz) 3.6864 4 4.9152 5 bit rate (bits/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 ?0.25 150 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16 300 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 600 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16 1200 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 2400 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16 4800 0 23 0.00 0 25 0.16 0 31 0.00 0 32 ?1.36 9600 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73 19200 0 5 0.00 0 6 ?6.99 0 7 0.00 0 7 1.73 31250 ? ? ? 0 3 0.00 0 4 ?1.70 0 4 0.00 38400 0 2 0.00 0 2 8.51 0 3 0.00 0 3 1.73 [legend] ? : a setting is available but error occurs
section 16 serial communication interface 3 (sci3) rev. 3.00 sep. 10, 2007 page 298 of 528 rej09b0216-0300 table 16.3 examples of brr settings for various bit rates (asynchronous mode) (2) operating frequency (mhz) 6 6.144 7.3728 bit rate (bit/s) n n error (%) n n error (%) n n error (%) 110 2 106 ?0.44 2 108 0.08 2 130 ?0.07 150 2 77 0.16 2 79 0.00 2 95 0.00 300 1 155 0.16 1 159 0.00 1 191 0.00 600 1 77 0.16 1 79 0.00 1 95 0.00 1200 0 155 0.16 0 159 0.00 0 191 0.00 2400 0 77 0.16 0 79 0.00 0 95 0.00 4800 0 38 0.16 0 39 0.00 0 47 0.00 9600 0 19 ?2.34 0 19 0.00 0 23 0.00 19200 0 9 ?2.34 0 9 0.00 0 11 0.00 31250 0 5 0.00 0 5 2.40 0 6 5.33 38400 0 4 ?2.34 0 4 0.00 0 5 0.00 operating frequency (mhz) 8 9.8304 10 12 bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 141 0.03 2 174 ?0.26 2 177 ?0.25 2 212 0.03 150 2 103 0.16 2 127 0.00 2 129 0.16 2 155 0.16 300 1 207 0.16 1 255 0.00 2 64 0.16 2 77 0.16 600 1 103 0.16 1 127 0.00 1 129 0.16 1 155 0.16 1200 0 207 0.16 0 255 0.00 1 64 0.16 1 77 0.16 2400 0 103 0.16 0 127 0.00 0 129 0.16 0 155 0.16 4800 0 51 0.16 0 63 0.00 0 64 0.16 0 77 0.16 9600 0 25 0.16 0 31 0.00 0 32 ?1.36 0 38 0.16 19200 0 12 0.16 0 15 0.00 0 15 1.73 0 19 ?2.34 31250 0 7 0.00 0 9 ?1.70 0 9 0.00 0 11 0.00 38400 0 6 -6.99 0 7 0.00 0 7 1.73 0 9 ?2.34 [legend] ? : a setting is available but error occurs.
section 16 serial communication interface 3 (sci3) rev. 3.00 sep. 10, 2007 page 299 of 528 rej09b0216-0300 table 16.3 examples of brr settings for various bit rates (asynchronous mode) (3) operating frequency (mhz) 12.288 14 14.7456 16 bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 217 0.08 2 248 ?0.17 3 64 0.70 3 70 0.03 150 2 159 0.00 2 181 0.16 2 191 0.00 2 207 0.16 300 2 79 0.00 2 90 0.16 2 95 0.00 2 103 0.16 600 1 159 0.00 1 181 0.16 1 191 0.00 1 207 0.16 1200 1 79 0.00 1 90 0.16 1 95 0.00 1 103 0.16 2400 0 159 0.00 0 181 0.16 0 191 0.00 0 207 0.16 4800 0 79 0.00 0 90 0.16 0 95 0.00 0 103 0.16 9600 0 39 0.00 0 45 ?0.93 0 47 0.00 0 51 0.16 19200 0 19 0.00 0 22 ?0.93 0 23 0.00 0 25 0.16 31250 0 11 2.40 0 13 0.00 0 14 ?1.70 0 15 0.00 38400 0 9 0.00 ? ? ? 0 11 0.00 0 12 0.16 operating frequency (mhz) 18 20 bit rate (bit/s) n n error (%) n n error (%) 110 3 79 ?0.12 3 88 ?0.25 150 2 233 0.16 3 64 0.16 300 2 116 0.16 2 129 0.16 600 1 233 0.16 2 64 0.16 1200 1 116 0.16 1 129 0.16 2400 0 233 0.16 1 64 0.16 4800 0 116 0.16 0 129 0.16 9600 0 58 ?0.96 0 64 0.16 19200 0 28 1.02 0 32 ?1.36 31250 0 17 0.00 0 19 0.00 38400 0 14 ?2.34 0 15 1.73 [legend] ?: a setting is available but error occurs.
section 16 serial communication interface 3 (sci3) rev. 3.00 sep. 10, 2007 page 300 of 528 rej09b0216-0300 table 16.4 maximum bit rate for each frequency (asynchronous mode) (mhz) maximum bit rate (bit/s) n n (mhz) maximum bit rate (bit/s) n n 2 62500 0 0 8 250000 0 0 2.097152 65536 0 0 9.8304 307200 0 0 2.4576 76800 0 0 10 312500 0 0 3 93750 0 0 12 375000 0 0 3.6864 115200 0 0 12.288 384000 0 0 4 125000 0 0 14 437500 0 0 4.9152 153600 0 0 14.7456 460800 0 0 5 156250 0 0 16 500000 0 0 6 187500 0 0 17.2032 537600 0 0 6.144 192000 0 0 18 562500 0 0 7.3728 230400 0 0 20 625000 0 0
section 16 serial communication interface 3 (sci3) rev. 3.00 sep. 10, 2007 page 301 of 528 rej09b0216-0300 table 16.5 examples of brr settings for various bit rates (clock synchronous mode) (1) operating frequency (mhz) 2 4 8 10 16 bit rate (bit/s) n n n n n n n n n n 110 3 70 ? ? ? ? ? ? 250 2 124 2 249 3 124 ? ? 3 249 500 1 249 2 124 2 249 ? ? 3 124 1k 1 124 1 249 2 124 ? ? 2 249 2.5k 0 199 1 99 1 199 1 249 2 99 5k 0 99 0 199 1 99 1 124 1 199 10k 0 49 0 99 0 199 0 249 1 99 25k 0 19 0 39 0 79 0 99 0 159 50k 0 9 0 19 0 39 0 49 0 79 100k 0 4 0 9 0 19 0 24 0 39 250k 0 1 0 3 0 7 0 9 0 15 500k 0 0 * 0 1 0 3 0 4 0 7 1m 0 0 * 0 1 ? ? 0 3 2m 0 0 * ? ? 0 1 2.5m 0 0 * ? ? 4m 0 0 * [legend] blank: no setting is available. ?: a setting is available but error occurs. * : continuous transfer is not possible.
section 16 serial communication interface 3 (sci3) rev. 3.00 sep. 10, 2007 page 302 of 528 rej09b0216-0300 table 16.5 examples of brr settings for various bit rates (clock synchronous mode) (2) operating frequency (mhz) 18 20 bit rate (bit/s) n n n n 110 ? ? ? ? 250 ? ? ? ? 500 3 140 3 155 1k 3 69 3 77 2.5k 2 112 2 124 5k 1 224 1 249 10k 1 112 1 124 25k 0 179 0 199 50k 0 89 0 99 100k 0 44 0 49 250k 0 17 0 19 500k 0 8 0 9 1m 0 4 0 4 2m ? ? ? ? 2.5m ? ? 0 1 4m ? ? ? ? [legend] blank: no setting is available. ?: a setting is available but error occurs. * : continuous transfer is not possible.
section 16 serial communication interface 3 (sci3) rev. 3.00 sep. 10, 2007 page 303 of 528 rej09b0216-0300 16.4 operation in as ynchronous mode figure 16.2 shows the general format for asynchronous serial communication. one character (or frame) consists of a start bit (low level), followed by data (in lsb-first order), a parity bit (high or low level), and finally stop bits (high level). inside the sci3, the transmitter and receiver are independent units, enabling full-duplex. both the transmitter and the receiver also have a double- buffered structure, so data can be read or written during transmission or reception, enabling continuous data transfer. lsb start bit msb mark state stop bit transmit/receive data 1 serial data parity bit 1 bit 1 or 2 bits 7 or 8 bits 1 bit or none one unit of transfer data (character or frame) figure 16.2 data format in asynchronous communication 16.4.1 clock either an internal clock generated by the on-chip baud rate generator or an external clock input at the sck3 pin can be selected as the sci3?s serial clock, according to the setting of the com bit in smr and the cke0 and cke1 bits in scr3. when an external clock is input at the sck3 pin, the clock frequency should be 16 times the bit rate used. when the sci3 is operated on an internal clock, the clock can be output from the sck3 pin. the frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 16.3. 0 1 character (frame) d0 d1 d2 d3 d4 d5 d6 d7 0/1 11 clock serial data figure 16.3 relationship between output clock and transfer data phase (asynchronous mode) (example with 8-bit data, parity, two stop bits)
section 16 serial communication interface 3 (sci3) rev. 3.00 sep. 10, 2007 page 304 of 528 rej09b0216-0300 16.4.2 sci3 initialization before transmitting and receiving data, you should first clear the te and re bits in scr3 to 0, then initialize the sci3 as described below. when the operating mode, or transfer format, is changed for example, the te and re bits must be cleared to 0 before making the change using the following procedure. when the te bit is cleared to 0, the tdre flag is set to 1. note that clearing the re bit to 0 does not initialize the contents of the rdrf, per, fer, and oer flags, or the contents of rdr. when the external clock is used in asynchronous mode, the clock must be supplied even during initialization. wait start initialization set data transfer format in smr [1] set cke1 and cke0 bits in scr3 no yes set value in brr clear te and re bits in scr3 to 0 [2] [3] set te and re bits in scr3 to 1, and set rie, tie, teie, and mpie bits. for transmit (te=1), also set the txd bit in pmr1. [4] 1-bit interval elapsed? [1] set the clock selection in scr3. be sure to clear bits rie, tie, teie, and mpie, and bits te and re, to 0. when the clock output is selected in asynchronous mode, clock is output immediately after cke1 and cke0 settings are made. when the clock output is selected at reception in clocked synchronous mode, clock is output immediately after cke1, cke0, and re are set to 1. [2] set the data transfer format in smr. [3] write a value corresponding to the bit rate to brr. not necessary if an external clock is used. [4] wait at least one bit interval, then set the te bit or re bit in scr3 to 1. re settings enable the rxd pin to be used. for transmission, set the txd bit in pmr1 to 1 to enable the txd output pin to be used. also set the rie, tie, teie, and mpie bits, depending on whether interrupts are required. in asynchronous mode, the bits are marked at transmission and idled at reception to wait for the start bit. figure 16.4 sample sci3 initialization flowchart
section 16 serial communication interface 3 (sci3) rev. 3.00 sep. 10, 2007 page 305 of 528 rej09b0216-0300 16.4.3 data transmission figure 16.5 shows an example of operation for transmission in asynchronous mode. in transmission, the sci3 operates as described below. 1. the sci3 monitors the tdre flag in ssr. if th e flag is cleared to 0, the sci3 recognizes that data has been written to tdr, and transfers the data from tdr to tsr. 2. after transferring data from tdr to tsr, the sci3 sets the tdre flag to 1 and starts transmission. if the tie bit is set to 1 at this time, a txi interrupt request is generated. continuous transmission is possible because the tx i interrupt routine write s next transmit data to tdr before transmission of the current transmit data has been completed. 3. the sci3 checks the tdre flag at the timing for sending the stop bit. 4. if the tdre flag is 0, the data is transferred from tdr to tsr, the stop bit is sent, and then serial transmission of the next frame is started. 5. if the tdre flag is 1, the tend flag in ssr is set to 1, the stop bit is sent, and then the ?mark state? is entered, in which 1 is output. if the teie bit in scr3 is set to 1 at this time, a tei interrupt request is generated. 6. figure 16.6 shows a sample flowchart for transmission in asynchronous mode. 1 frame start bit start bit transmit data transmit data parity bit stop bit parity bit stop bit mark state 1 frame 0 1d0d1d70/11 11 0d0d1 d70/1 serial data tdre tend lsi operation txi interrupt request generated tdre flag cleared to 0 user processing data written to tdr txi interrupt request generated tei interrupt request generated figure 16.5 example of sci3 transmission in asynchronous mode (8-bit data, parity, one stop bit)
section 16 serial communication interface 3 (sci3) rev. 3.00 sep. 10, 2007 page 306 of 528 rej09b0216-0300 no yes start transmission read tdre flag in ssr [1] write transmit data to tdr yes no no yes read tend flag in ssr [2] no yes [3] clear pdr to 0 and set pcr to 1 clear te bit in scr3 to 0 tdre = 1 all data transmitted? tend = 1 break output? [1] read ssr and check that the tdre flag is set to 1, then write transmit data to tdr. when data is written to tdr, the tdre flag is automaticaly cleared to 0. [2] to continue serial transmission, read 1 from the tdre flag to confirm that writing is possible, then write data to tdr. when data is written to tdr, the tdre flag is automaticaly cleared to 0. [3] to output a break in serial transmission, after setting pcr to 1 and pdr to 0, clear txd in pmr1 to 0, then clear the te bit in scr3 to 0. figure 16.6 sample serial transmission data flowchart (asynchronous mode)
section 16 serial communication interface 3 (sci3) rev. 3.00 sep. 10, 2007 page 307 of 528 rej09b0216-0300 16.4.4 serial da ta reception figure 16.7 shows an example of operation fo r reception in asynchronous mode. in serial reception, the sci3 operates as described below. 1. the sci3 monitors the communication line. if a start bit is detected, the sci3 performs internal synchronization, receives receive data in rsr, and checks the parity bit and stop bit. 2. if an overrun error occurs (when reception of th e next data is completed while the rdrf flag is still set to 1), the oer bit in ssr is set to 1. if the rie bit in scr3 is set to 1 at this time, an eri interrupt request is generated. recei ve data is not transferred to rdr. 3. if a parity error is detected, the per bit in ssr is set to 1 and receive data is transferred to rdr. if the rie bit in scr3 is set to 1 at this time, an eri interrupt request is generated. 4. if a framing error is detected (when the stop bit is 0), the fer bit in ssr is set to 1 and receive data is transferred to rdr. if the rie bit in scr3 is set to 1 at this time, an eri interrupt request is generated. 5. if reception is completed succe ssfully, the rdrf bit in ssr is set to 1, and receive data is transferred to rdr. if the rie bit in scr3 is set to 1 at this time, an rxi interrupt request is generated. continuous reception is possible becau se the rxi interrupt r outine reads the receive data transferred to rdr before reception of the next receive data has been completed. 1 frame start bit start bit receive data receive data parity bit stop bit parity bit stop bit mark state (idle state) 1 frame 0 1d0d1d70/11 01 0d0d1 d70/1 serial data rdrf fer lsi operation user processing rdrf cleared to 0 rdr data read framing error processing rxi request 0 stop bit detected eri request in response to framing error figure 16.7 example of sci3 r eception in asynchronous mode (8-bit data, parity, one stop bit)
section 16 serial communication interface 3 (sci3) rev. 3.00 sep. 10, 2007 page 308 of 528 rej09b0216-0300 table 16.6 shows the states of the ssr status flag s and receive data handling when a receive error is detected. if a receive error is detected, the rd rf flag retains its state before receiving data. reception cannot be resumed while a receive error fl ag is set to 1. accordingly, clear the oer, fer, per, and rdrf bits to 0 before resuming reception. figure 16.8 shows a sample flow chart for serial data reception. table 16.6 ssr status flags and receive data handling ssr status flag rdrf * oer fer per receive data receive error type 1 1 0 0 lost overrun error 0 0 1 0 transferred to rdr framing error 0 0 0 1 transferred to rdr parity error 1 1 1 0 lost overrun error + framing error 1 1 0 1 lost overrun error + parity error 0 0 1 1 transferred to rdr framing error + parity error 1 1 1 1 lost overrun error + framing error + parity error note: * the rdrf flag retains the state it had before data reception.
section 16 serial communication interface 3 (sci3) rev. 3.00 sep. 10, 2007 page 309 of 528 rej09b0216-0300 yes no start reception [1] no yes read rdrf flag in ssr [2] [3] clear re bit in scr3 to 0 read oer, per, and fer flags in ssr error processing (continued on next page) [4] read receive data in rdr yes no oer+per+fer = 1 rdrf = 1 all data received? [1] read the oer, per, and fer flags in ssr to identify the error. if a receive error occurs, performs the appropriate error processing. [2] read ssr and check that rdrf = 1, then read the receive data in rdr. the rdrf flag is cleared automatically. [3] to continue serial reception, before the stop bit for the current frame is received, read the rdrf flag and read rdr. the rdrf flag is cleared automatically. [4] if a receive error occurs, read the oer, per, and fer flags in ssr to identify the error. after performing the appropriate error processing, ensure that the oer, per, and fer flags are all cleared to 0. reception cannot be resumed if any of these flags are set to 1. in the case of a framing error, a break can be detected by reading the value of the input port corresponding to the rxd pin. (a) figure 16.8 sample serial reception data flowchart (asynchronous mode) (1)
section 16 serial communication interface 3 (sci3) rev. 3.00 sep. 10, 2007 page 310 of 528 rej09b0216-0300 (a) error processing parity error processing yes no clear oer, per, and fer flags in ssr to 0 no yes no yes framing error processing no yes overrun error processing oer = 1 fer = 1 break? per = 1 [4] figure 16.8 sample serial reception data flowchart (asynchronous mode) (2)
section 16 serial communication interface 3 (sci3) rev. 3.00 sep. 10, 2007 page 311 of 528 rej09b0216-0300 16.5 operation in clock synchronous mode figure 16.9 shows the general format for clock synchronous communication. in clock synchronous mode, data is transmitted or received synchronous with clock pulses. a single character in the transmit data consists of the 8-bit data starting from the lsb. in clock synchronous serial communication, data on the transmission line is output from one falling edge of the synchronization clock to the ne xt. in clock synchronous mode, the sci3 receives data in synchronous with the rising edge of the synchronization clock. after 8-bit data is output, the transmission line holds the msb state. in clock synchronous mode, no parity or multiprocessor bit is added. inside the sci3, the transmitter and r eceiver are independent units, enabling full-duplex communication through the use of a common clock. both the transmitter and the receiver also have a double-buffered structure, so data can be read or written during transmission or reception, enabling continuous data transfer. don?t care don?t care one unit of transfer data (character or frame) 8 bits bit 0 serial data synchronization clock bit 1 bit 3 bit 4 bit 5 lsb msb bit 2 bit 6 bit 7 * * note: * high except in continuous transfer figure 16.9 data format in clock synchronous communication 16.5.1 clock either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the sck3 pin can be selected, according to the setting of the com bit in smr and cke0 and cke1 bits in scr3. when the sci3 is operated on an internal clock, the synchronization clock is output from the sck3 pin. eight synchronization clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. 16.5.2 sci3 initialization before transmitting and receiving data, the sci3 should be initialized as described in a sample flowchart in figure 16.4.
section 16 serial communication interface 3 (sci3) rev. 3.00 sep. 10, 2007 page 312 of 528 rej09b0216-0300 16.5.3 serial data transmission figure 16.10 shows an example of sci3 operation for transmission in clock synchronous mode. in serial transmission, the sci3 operates as described below. 1. the sci3 monitors the tdre flag in ssr, and if the flag is 0, the sc i3 recognizes that data has been written to tdr, and transfers the data from tdr to tsr. 2. the sci3 sets the tdre flag to 1 and starts tr ansmission. if the tie bit in scr3 is set to 1 at this time, a transmit data empty interrupt (txi) is generated. 3. 8-bit data is sent from the txd pin synchronized with the output clock when output clock mode has been specified, and synchronized with the input clock when use of an external clock has been specified. serial data is transmitted sequentially from the lsb (bit 0), from the txd pin. 4. the sci3 checks the tdre flag at the timing for sending the msb (bit 7). 5. if the tdre flag is cleared to 0, data is tr ansferred from tdr to tsr, and serial transmission of the next frame is started. 6. if the tdre flag is set to 1, the tend flag in ssr is set to 1, and the tdre flag maintains the output state of the last bit. if the teie bit in scr3 is set to 1 at this time, a tei interrupt request is generated. 7. the sck3 pin is fixed high at the end of transmission. figure 16.11 shows a sample flow chart for serial data transmission. even if the tdre flag is cleared to 0, transmission will not start while a recei ve error flag (oer, fer, or per) is set to 1. make sure that the receive error flags are cleared to 0 before starting transmission. serial clock serial data bit 1 bit 0 bit 7 bit 0 1 frame 1 frame bit 1 bit 6 bit 7 tdre tend lsi operation user processing txi interrupt request generated data written to tdr tdre flag cleared to 0 txi interrupt request generated tei interrupt request generated figure 16.10 example of sci3 transmission in clock synchronous mode
section 16 serial communication interface 3 (sci3) rev. 3.00 sep. 10, 2007 page 313 of 528 rej09b0216-0300 no yes start transmission read tdre flag in ssr [1] write transmit data to tdr no yes no yes read tend flag in ssr [2] clear te bit in scr3 to 0 tdre = 1 all data transmitted? tend = 1 [1] read ssr and check that the tdre flag is set to 1, then write transmit data to tdr. when data is written to tdr, the tdre flag is automatically cleared to 0 and clocks are output to start the data transmission. [2] to continue serial transmission, be sure to read 1 from the tdre flag to confirm that writing is possible, then write data to tdr. when data is written to tdr, the tdre flag is automatically cleared to 0. figure 16.11 sample serial transmission flowchart (clock synchronous mode)
section 16 serial communication interface 3 (sci3) rev. 3.00 sep. 10, 2007 page 314 of 528 rej09b0216-0300 16.5.4 serial data reception (clock synchronous mode) figure 16.12 shows an example of sci3 operation for reception in clock synchronous mode. in serial reception, the sci3 operates as described below. 1. the sci3 performs internal initialization sync hronous with a synchron ization cloc k input or output, starts receiving data. 2. the sci3 stores the receive data in rsr. 3. if an overrun error occurs (when reception of th e next data is completed while the rdrf flag in ssr is still set to 1), the oer bit in ssr is set to 1. if the rie bit in scr3 is set to 1 at this time, an eri interrupt request is generated, r eceive data is not transferred to rdr, and the rdrf flag remains to be set to 1. 4. if reception is completed succe ssfully, the rdrf bit in ssr is set to 1, and receive data is transferred to rdr. if the rie bit in scr3 is set to 1 at this time, an rxi interrupt request is generated. serial clock serial data 1 frame 1 frame bit 0 bit 7 bit 7 bit 0 bit 1 bit 6 bit 7 rdrf oer lsi operation user processing rxi interrupt request generated rdr data read rdrf flag cleared to 0 rxi interrupt request generated eri interrupt request generated by overrun error overrun error processing rdr data has not been read (rdrf = 1) figure 16.12 example of sci3 r eception in clock synchronous mode
section 16 serial communication interface 3 (sci3) rev. 3.00 sep. 10, 2007 page 315 of 528 rej09b0216-0300 reception cannot be resumed while a receive error fl ag is set to 1. accordingly, clear the oer, fer, per, and rdrf bits to 0 before resuming reception. figure 16.13 shows a sample flow chart for serial data reception. yes no start reception [1] [4] no yes read rdrf flag in ssr [2] [3] clear re bit in scr3 to 0 error processing (continued below) read receive data in rdr yes no oer = 1 rdrf = 1 all data received? read oer flag in ssr error processing overrun error processing clear oer flag in ssr to 0 [4] [1] read the oer flag in ssr to determine if there is an error. if an overrun error has occurred, execute overrun error processing. [2] read ssr and check that the rdrf flag is set to 1, then read the receive data in rdr. when data is read from rdr, the rdrf flag is automatically cleared to 0. [3] to continue serial reception, before the msb (bit 7) of the current frame is received, reading the rdrf flag and reading rdr should be finished. when data is read from rdr, the rdrf flag is automatically cleared to 0. [4] if an overrun error occurs, read the oer flag in ssr, and after performing the appropriate error processing, clear the oer flag to 0. reception cannot be resumed if the oer flag is set to 1. figure 16.13 sample s erial reception fl owchart (clock synchronous mode)
section 16 serial communication interface 3 (sci3) rev. 3.00 sep. 10, 2007 page 316 of 528 rej09b0216-0300 16.5.5 simultaneous serial data transmission and reception figure 16.14 shows a sample flowchart for simulta neous serial transmit and receive operations. the following procedure should be used for simultaneous serial data transmit and receive operations. to switch from transmit mode to simultaneous transmit and receive mode, after checking that the sci3 has finished transmission and the tdre and tend flags are set to 1, clear te to 0. then simultaneously set te and re to 1 w ith a single instruction. to switch from receive mode to simultaneous transmit and receive mode , after checking that the sci3 has finished reception, clear re to 0. then after checking that the rdrf and receive error flags (oer, fer, and per) are cleared to 0, simultaneously se t te and re to 1 with a single instruction.
section 16 serial communication interface 3 (sci3) rev. 3.00 sep. 10, 2007 page 317 of 528 rej09b0216-0300 yes no start transmission/reception [3] error processing [4] read receive data in rdr yes no oer = 1 all data received? [1] read tdre flag in ssr no yes tdre = 1 write transmit data to tdr no yes rdrf = 1 read oer flag in ssr [2] read rdrf flag in ssr clear te and re bits in scr to 0 [1] read ssr and check that the tdre flag is set to 1, then write transmit data to tdr. when data is written to tdr, the tdre flag is automatically cleared to 0. [2] read ssr and check that the rdrf flag is set to 1, then read the receive data in rdr. when data is read from rdr, the rdrf flag is automatically cleared to 0. [3] to continue serial transmission/ reception, before the msb (bit 7) of the current frame is received, finish reading the rdrf flag, reading rdr. also, before the msb (bit 7) of the current frame is transmitted, read 1 from the tdre flag to confirm that writing is possible. then write data to tdr. when data is written to tdr, the tdre flag is automatically cleared to 0. when data is read from rdr, the rdrf flag is automatically cleared to 0. [4] if an overrun error occurs, read the oer flag in ssr, and after performing the appropriate error processing, clear the oer flag to 0. transmission/reception cannot be resumed if the oer flag is set to 1. for overrun error processing, see figure 16.13. figure 16.14 sample flowchar t of simultaneous serial tr ansmit and receive operations (clock synchronous mode)
section 16 serial communication interface 3 (sci3) rev. 3.00 sep. 10, 2007 page 318 of 528 rej09b0216-0300 16.6 multiprocessor comm unication function use of the multiprocessor communication function enables data transfer between a number of processors sharing communication lines by asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. when multiprocessor communication is performed, each receiving station is addressed by a unique id code. the serial communica tion cycle consists of two component cycles; an id transmission cycle that specifies the receiving station, and a data tr ansmission cycle. the multiprocessor bit is used to differentiate between the id transmission cycl e and the data transmission cycle. if the multiprocessor bit is 1, the cycle is an id transmission cycle; if the multiprocessor bit is 0, the cycle is a data transmission cycle. figure 16.15 shows an example of inter-processor communication using the multiprocessor format. the transmitting station first sends the id code of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. it then sends transmit data as data with a 0 multiprocessor bit added. when data with a 1 multiprocessor bit is received, the receiving station compares that data with its own id. the station whose id matc hes then receives the data sent next. stations whose ids do not match continue to skip data until data with a 1 multiprocessor bit is again received. the sci3 uses the mpie bit in scr3 to implement this function. when the mpie bit is set to 1, transfer of receive data from rs r to rdr, error flag detection, and setting the ssr status flags, rdrf, fer, and oer, to 1, are inhibited until data with a 1 multiprocessor bit is received. on reception of a receive character with a 1 multiprocessor bit, the mpbr bit in ssr is set to 1 and the mpie bit is automatically cleared, thus normal reception is resumed. if the rie bit in scr3 is set to 1 at this time, an rxi interrupt is generated. when the multiprocessor format is selected, the parity bit setting is rendered invalid. all other bit settings are the same as those in normal asynchronous mode. the clock used for multiprocessor communication is the same as that in normal asynchronous mode.
section 16 serial communication interface 3 (sci3) rev. 3.00 sep. 10, 2007 page 319 of 528 rej09b0216-0300 transmitting station receiving station a receiving station b receiving station c receiving station d (id = 01) (id = 02) (id = 03) (id = 04) serial transmission line serial data id transmission cycle = receiving station specification data transmission cycle = data transmission to receiving station specified by id (mpb = 1) (mpb = 0) h'01 h'aa legend mpb: multiprocessor bit figure 16.15 example of inter-processor communication using mu ltiprocessor format (transmission of data h'aa to receiving station a) 16.6.1 multiprocessor serial data transmission figure 16.16 shows a sample flowchart for multiprocessor serial data transmission. for an id transmission cycle, set the mpbt bit in ssr to 1 before transmission. for a data transmission cycle, clear the mpbt bit in ssr to 0 before transmission. all other sci3 operations are the same as those in asynchronous mode.
section 16 serial communication interface 3 (sci3) rev. 3.00 sep. 10, 2007 page 320 of 528 rej09b0216-0300 no yes start transmission read tdre flag in ssr [1] set mpbt bit in ssr yes no no yes read tend flag in ssr [2] no yes [3] clear pdr to 0 and set pcr to 1 clear te bit in scr3 to 0 tdre = 1 all data transmitted? tend = 1 break output? write transmit data to tdr [1] read ssr and check that the tdre flag is set to 1, set the mpbt bit in ssr to 0 or 1, then write transmit data to tdr. when data is written to tdr, the tdre flag is automatically cleared to 0. [2] to continue serial transmission, be sure to read 1 from the tdre flag to confirm that writing is possible, then write data to tdr. when data is written to tdr, the tdre flag is automatically cleared to 0. [3] to output a break in serial transmission, set the port pcr to 1, clear pdr to 0, then clear the te bit in scr3 to 0. figure 16.16 sample multiprocessor serial transmission flowchart
section 16 serial communication interface 3 (sci3) rev. 3.00 sep. 10, 2007 page 321 of 528 rej09b0216-0300 16.6.2 multiprocessor s erial data reception figure 16.17 shows a sample flowchart for multiprocessor serial data reception. if the mpie bit in scr3 is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. on receiving data with a 1 multiprocessor bit, the receive data is tr ansferred to rdr. an rxi interrupt request is generated at this time. all other sci3 operations are the same as those in asynchronous mode. figure 16.18 shows an example of sci3 operation for multiprocessor format reception.
section 16 serial communication interface 3 (sci3) rev. 3.00 sep. 10, 2007 page 322 of 528 rej09b0216-0300 yes no start reception no yes [4] clear re bit in scr3 to 0 error processing (continued on next page) [5] yes no fer+oer = 1 rdrf = 1 all data received? set mpie bit in scr3 to 1 [1] [2] read oer and fer flags in ssr read rdrf flag in ssr [3] read receive data in rdr no yes [a] this station?s id? read oer and fer flags in ssr yes no read rdrf flag in ssr no yes fer+oer = 1 read receive data in rdr rdrf = 1 [1] set the mpie bit in scr3 to 1. [2] read oer and fer in ssr to check for errors. receive error processing is performed in cases where a receive error occurs. [3] read ssr and check that the rdrf flag is set to 1, then read the receive data in rdr and compare it with this station?s id. if the data is not this station?s id, set the mpie bit to 1 again. when data is read from rdr, the rdrf flag is automatically cleared to 0. [4] read ssr and check that the rdrf flag is set to 1, then read the data in rdr. [5] if a receive error occurs, read the oer and fer flags in ssr to identify the error. after performing the appropriate error processing, ensure that the oer and fer flags are all cleared to 0. reception cannot be resumed if either of these flags is set to 1. in the case of a framing error, a break can be detected by reading the rxd pin value. figure 16.17 sample multiprocesso r serial reception flowchart (1)
section 16 serial communication interface 3 (sci3) rev. 3.00 sep. 10, 2007 page 323 of 528 rej09b0216-0300 error processing yes no clear oer, and fer flags in ssr to 0 no yes no yes framing error processing overrun error processing oer = 1 fer = 1 break? [5] [a] figure 16.17 sample multiprocesso r serial reception flowchart (2)
section 16 serial communication interface 3 (sci3) rev. 3.00 sep. 10, 2007 page 324 of 528 rej09b0216-0300 1 frame start bit start bit receive data (id1) receive data (data1) mpb mpb stop bit stop bit mark state (idle state) 1 frame 0 1d0d1d711 11 0d0d1 d7 id1 0 serial data mpie rdrf rdr value rdr value lsi operation rxi interrupt request mpie cleared to 0 user processing rdrf flag cleared to 0 rxi interrupt request is not generated, and rdr retains its state rdr data read when data is not this station's id, mpie is set to 1 again 1 frame start bit start bit receive data (id2) receive data (data2) mpb mpb stop bit stop bit mark state (idle state) 1 frame 0 1d0d1d711 11 0 (a) when data does not match this receiver's id (b) when data matches this receiver's id d0 d1 d7 id2 data2 id1 0 serial data mpie rdrf lsi operation rxi interrupt request mpie cleared to 0 user processing rdrf flag cleared to 0 rxi interrupt request rdrf flag cleared to 0 rdr data read when data is this station's id, reception is continued rdr data read mpie set to 1 again figure 16.18 example of sci3 r eception using multiprocessor format (example with 8-bit data, multiprocessor bit, one stop bit)
section 16 serial communication interface 3 (sci3) rev. 3.00 sep. 10, 2007 page 325 of 528 rej09b0216-0300 16.7 interrupts sci3 creates the following six interrupt requests: transmission end, transmit data empty, receive data full, and receive errors (overrun error, fram ing error, and parity error). table 16.7 shows the interrupt sources. table 16.7 sci3 interrupt requests interrupt requests abbrevi ation interrupt sources receive data full rxi setting rdrf in ssr transmit data empty txi setting tdre in ssr transmission end tei setting tend in ssr receive error eri setting oer, fer, and per in ssr the initial value of the tdre flag in ssr is 1. thus, when the tie bit in scr3 is set to 1 before transferring the transmit data to tdr, a txi interrupt request is generated even if the transmit data is not ready. the initial value of the tend flag in ssr is 1. thus, when the teie bit in scr3 is set to 1 before transferring the transmit data to tdr, a tei interrupt request is generated even if the transmit data has not been sent. it is possible to make use of the most of these interrupt requests efficiently by transferring the transmit data to tdr in the interrupt routine. to prevent the generation of these interrupt requests (txi and tei), set the enable bits (tie and teie) that correspond to these interrupt requests to 1, after transferring the transmit data to tdr.
section 16 serial communication interface 3 (sci3) rev. 3.00 sep. 10, 2007 page 326 of 528 rej09b0216-0300 16.8 usage notes 16.8.1 break detectio n and processing when framing error detection is performed, a break can be detected by reading the rxd pin value directly. in a break, the input from the rxd pin becomes all 0s, setting the fer flag, and possibly the per flag. note that as the sci3 continues the receive oper ation after receiving a break, even if the fer flag is cleared to 0, it will be set to 1 again. 16.8.2 mark state and break sending when the txd or txd2 bit in pmr1 is 1, the txd pin is used as an i/o port whose direction (input or output) and level are determined by pcr and pdr. this can be used to set the txd pin to mark state (high level) or send a break during serial data transmission. to maintain the communication line at mark state until te is set to 1, set both pcr and pdr to 1, and then set the txd bit to 1. at this point, the txd pin becomes an i/o port, and 1 is output from the txd pin. to send a break during serial transmission, first set pcr to 1 and clear pdr to 0, and then set the txd bit to 1. at this point, the txd pin becomes an i/o port regardless of the current transmission state, and 0 is output from the txd pin. 16.8.3 receive error flags and transmit op erations (clock sync hronous mode only) transmission cannot be started when a receive error fl ag (oer, per, or fer) is set to 1, even if the tdre flag is cleared to 0. be sure to cl ear the receive error flags to 0 before starting transmission. note also that receive error flags cannot be cleared to 0 even if the re bit is cleared to 0.
section 16 serial communication interface 3 (sci3) rev. 3.00 sep. 10, 2007 page 327 of 528 rej09b0216-0300 16.8.4 receive data sampling timing and reception margin in asynchronous mode in asynchronous mode, the sci3 operates on a basic clock with a frequency of 16 times the transfer rate. in reception, the sci3 samples the fa lling edge of the start bit using the basic clock, and performs internal synchroniza tion. receive data is latched inte rnally at the rising edge of the 8th pulse of the basic clock as shown in figure 16.19. thus, the reception margin in asynchronous mode is given by formula (1) below. m = (0.5 ? ) ? ? (l ? 0.5) f 100(%) ? ? ? ? ? ? 1 2n d ? 0.5 n ... formula (1) [legend] n: ratio of bit rate to clock (n = 16) d: clock duty (d = 0.5 to 1.0) l: frame length (l = 9 to 12) f: absolute value of clock rate deviation assuming values of f (absolute value of clock rate deviation) = 0 and d (clock duty) = 0.5 in formula (1), the reception margin can be given by the formula. m = {0.5 ? 1/(2 16)} 100 [%] = 46.875% however, this is only the computed value, and a margin of 20% to 30% should be allowed for in system design. internal basic clock 16 clocks 8 clocks receive data (rxd) synchronization sampling timing start bit d0 d1 data sampling timing 15 0 7 15 0 0 7 figure 16.19 receive data samplin g timing in asynchronous mode
section 16 serial communication interface 3 (sci3) rev. 3.00 sep. 10, 2007 page 328 of 528 rej09b0216-0300
section 17 i 2 c bus interface 2 (iic2) ifiic10a_000020020200 rev. 3.00 sep. 10, 2007 page 329 of 528 rej09b0216-0300 section 17 i 2 c bus interface 2 (iic2) the i 2 c bus interface 2 conforms to and provides a subset of the philips i 2 c bus (inter-ic bus) interface functions. the register c onfiguration that controls the i 2 c bus differs partly from the philips configuration, however. figure 17.1 shows a block diagram of the i 2 c bus interface 2. figure 17.2 shows an example of i/o pin connections to external circuits. 17.1 features ? selection of i 2 c format or clock synchronous serial format ? continuous transmission/reception since the shift register, transmit data register, and receive data register are independent from each other, the continuous transm ission/reception can be performed. i 2 c bus format ? start and stop conditions generated automatically in master mode ? selection of acknowledge out put levels when receiving ? automatic loading of acknow ledge bit when transmitting ? bit synchronization/wait function in master mode, the state of scl is monitored per bit, and the timing is synchronized automatically. if transmission/reception is not yet possible, set the scl to low until preparations are completed. ? six interrupt sources transmit data empty (including slave-address match), transmit e nd, receive data full (including slave-address match), arbitration lost, nack detection, and stop condition detection ? direct bus drive two pins, scl and sda pins, function as nmos open-drain outputs when the bus drive function is selected. clock synchronous format ? four interrupt sources transmit-data-empty, transmit-end, r eceive-data-full, and overrun error
section 17 i 2 c bus interface 2 (iic2) rev. 3.00 sep. 10, 2007 page 330 of 528 rej09b0216-0300 scl iccr1 transfer clock generation circuit address comparator interrupt generator interrupt request bus state decision circuit arbitration decision circuit noise canceler noise canceler output control output control transmission/ reception control circuit iccr2 icmr icsr icier icdrr icdrs icdrt i 2 c bus control register 1 i 2 c bus control register 2 i 2 c bus mode register i 2 c bus status register i 2 c bus interrupt enable register i 2 c bus transmit data register i 2 c bus receive data register i 2 c bus shift register slave address register [legend] iccr1: iccr2: icmr: icsr: icier: icdrt: icdrr: icdrs: sar: sar sda internal data bus figure 17.1 block diagram of i 2 c bus interface 2
section 17 i 2 c bus interface 2 (iic2) rev. 3.00 sep. 10, 2007 page 331 of 528 rej09b0216-0300 vcc vcc scl in scl out scl sda in sda out sda scl (master) (slave 1) (slave 2) sda scl in scl out scl sda in sda out sda scl in scl out scl sda in sda out sda figure 17.2 external circuit connections of i/o pins 17.2 input/output pins table 17.1 summarizes the input/output pins used by the i 2 c bus interface 2. table 17.1 i 2 c bus interface pins name abbreviation i/o function serial clock scl i/o iic serial clock input/output serial data sda i/o iic serial data input/output
section 17 i 2 c bus interface 2 (iic2) rev. 3.00 sep. 10, 2007 page 332 of 528 rej09b0216-0300 17.3 register descriptions the i 2 c bus interface 2 has the following registers: ? i 2 c bus control register 1 (iccr1) ? i 2 c bus control register 2 (iccr2) ? i 2 c bus mode register (icmr) ? i 2 c bus interrupt enable register (icier) ? i 2 c bus status register (icsr) ? i 2 c bus slave address register (sar) ? i 2 c bus transmit data register (icdrt) ? i 2 c bus receive data register (icdrr) ? i 2 c bus shift register (icdrs) 17.3.1 i 2 c bus control register 1 (iccr1) iccr1 enables or disables the i 2 c bus interface 2, controls transm ission or reception, and selects master or slave mode, transmission or reception, and transfer clock frequency in master mode. bit bit name initial value r/w description 7 ice 0 r/w i 2 c bus interface enable 0: this module is halted. (scl and sda pins are set to port function.) 1: this bit is enabled for transfer operations. (scl and sda pins are bus drive state.) 6 rcvd 0 r/w reception disable this bit enables or disables the next operation when trs is 0 and icdrr is read. 0: enables next reception 1: disables next reception
section 17 i 2 c bus interface 2 (iic2) rev. 3.00 sep. 10, 2007 page 333 of 528 rej09b0216-0300 bit bit name initial value r/w description 5 4 mst trs 0 0 r/w r/w master/slave select transmit/receive select in master mode with the i 2 c bus format, when arbitration is lost, mst and trs are both reset by hardware, causing a transition to slave receive mode. modification of the trs bit should be made between transfer frames. after data receive has been started in slave receive mode, when the first seven bits of the receive data agree with the slave address that is set to sar and the eighth bit is 1, trs is automatically set to 1. if an overrun error occurs in master mode with the clock synchronous serial format, mst is cleared to 0 and slave receive mode is entered. operating modes are described below according to mst and trs combination. when clock synchronous serial format is selected and mst is 1, clock is output. 00: slave receive mode 01: slave transmit mode 10: master receive mode 11: master transmit mode 3 2 1 0 cks3 cks2 cks1 cks0 0 0 0 0 r/w r/w r/w r/w transfer clock select 3 to 0 these bits should be set according to the necessary transfer rate (see table 17.2) in master mode. in slave mode, these bits are used for reservation of the setup time in transmit mode. the time is 10 t cyc when cks3 = 0 and 20 t cyc when cks3 = 1.
section 17 i 2 c bus interface 2 (iic2) rev. 3.00 sep. 10, 2007 page 334 of 528 rej09b0216-0300 table 17.2 transfer rate bit 3 bit 2 bit 1 bit 0 transfer rate cks3 cks2 cks1 cks0 clock = 5 mhz = 8 mhz = 10 mhz = 16 mhz = 20 mhz 0 /28 179 khz 286 khz 357 khz 571 khz 714 khz 0 1 /40 125 khz 200 khz 250 khz 400 khz 500 khz 0 /48 104 khz 167 khz 208 khz 333 khz 417 khz 0 1 1 /64 78.1 khz 125 khz 156 khz 250 khz 313 khz 0 /80 62.5 khz 100 khz 125 khz 200 khz 250 khz 0 1 /100 50.0 khz 80.0 khz 100 khz 160 khz 200 khz 0 /112 44.6 khz 71.4 khz 89.3 khz 143 khz 179 khz 0 1 1 1 /128 39.1 khz 62.5 khz 78.1 khz 125 khz 156 khz 0 /56 89.3 khz 143 khz 179 khz 286 khz 357 khz 0 1 /80 62.5 khz 100 khz 125 khz 200 khz 250 khz 0 /96 52.1 khz 83.3 khz 104 khz 167 khz 208 khz 0 1 1 /128 39.1 khz 62.5 khz 78.1 khz 125 khz 156 khz 0 /160 31.3 khz 50.0 khz 62.5 khz 100 khz 125 khz 0 1 /200 25.0 khz 40.0 khz 50.0 khz 80.0 khz 100 khz 0 /224 22.3 khz 35.7 khz 44.6 khz 71.4 khz 89.3 khz 1 1 1 1 /256 19.5 khz 31.3 khz 39.1 khz 62.5 khz 78.1 khz
section 17 i 2 c bus interface 2 (iic2) rev. 3.00 sep. 10, 2007 page 335 of 528 rej09b0216-0300 17.3.2 i 2 c bus control register 2 (iccr2) iccr1 issues start/stop conditions, manipulates the sda pin, monitors the scl pin, and controls reset in the control part of the i 2 c bus interface 2. bit bit name initial value r/w description 7 bbsy 0 r/w bus busy this bit enables to confirm whether the i 2 c bus is occupied or released and to issue start/stop conditions in master mode. with the clock synchronous serial format, this bit has no meaning. with the i 2 c bus format, this bit is set to 1 when the sda level changes from high to low under the condition of scl = high, assuming that the start condition has been issued. this bit is cleared to 0 when the sda level changes from low to high under the condition of scl = high, assuming that the stop condition has been issued. write 1 to bbsy and 0 to scp to issue a start condition. follow this procedure when also re- transmitting a start condition. write 0 in bbsy and 0 in scp to issue a stop condition. to issue start/stop conditions, use the mov instruction. 6 scp 1 w start/stop issue condition disable the scp bit controls the issue of start/stop conditions in master mode. to issue a start condition, write 1 in bbsy and 0 in scp. a retransmit start condition is issued in the same way. to issue a stop condition, write 0 in bbsy and 0 in scp. this bit is always read as 1. if 1 is written, the data is not stored. 5 sdao 1 r/w sda output value control this bit is used with sdaop when modifying output level of sda. this bit should not be manipulated during transfer. 0: when reading, sda pin outputs low. when writing, sda pin is changed to output low. 1: when reading, sda pin outputs high. when writing, sda pin is changed to output hi-z (outputs high by external pull-up resistance).
section 17 i 2 c bus interface 2 (iic2) rev. 3.00 sep. 10, 2007 page 336 of 528 rej09b0216-0300 bit bit name initial value r/w description 4 sdaop 1 r/w sdao write protect this bit controls change of output level of the sda pin by modifying the sdao bit. to change the output level, clear sdao and sdaop to 0 or set sdao to 1 and clear sdaop to 0 by the mov instruction. this bit is always read as 1. 3 sclo 1 r this bit monitors scl output level. when sclo is 1, scl pin outputs high. when sclo is 0, scl pin outputs low. 2 ? 1 ? reserved this bit is always read as 1, and cannot be modified. 1 iicrst 0 r/w iic control part reset this bit resets the control part except for i 2 c registers. if this bit is set to 1 when hang-up occurs because of communication failure during i 2 c operation, i 2 c control part can be reset without setting ports and initializing registers. 0 ? 1 ? reserved this bit is always read as 1, and cannot be modified. 17.3.3 i 2 c bus mode register (icmr) icmr selects whether the msb or lsb is transferred first, performs master mode wait control, and selects the transfer bit count. bit bit name initial value r/w description 7 mls 0 r/w msb-first/lsb-first select 0: msb-first 1: lsb-first set this bit to 0 when the i 2 c bus format is used.
section 17 i 2 c bus interface 2 (iic2) rev. 3.00 sep. 10, 2007 page 337 of 528 rej09b0216-0300 bit bit name initial value r/w description 6 wait 0 r/w wait insertion bit in master mode with the i 2 c bus format, this bit selects whether to insert a wait after data transfer except the acknowledge bit. when wait is set to 1, after the fall of the clock for the final data bit, low period is extended for two transfer clocks. if wait is cleared to 0, data and acknowledge bits are transferred consecutively with no wait inserted. the setting of this bit is invalid in slave mode with the i 2 c bus format or with the clock synchronous serial format. 5, 4 ? all 1 ? reserved these bits are always read as 1, and cannot be modified. 3 bcwp 1 r/w bc write protect this bit controls the bc2 to bc0 modifications. when modifying bc2 to bc0, this bit should be cleared to 0 and use the mov instruction. in clock synchronous serial mode, bc should not be modified. 0: when writing, values of bc2 to bc0 are set. 1: when reading, 1 is always read. when writing, settings of bc2 to bc0 are invalid.
section 17 i 2 c bus interface 2 (iic2) rev. 3.00 sep. 10, 2007 page 338 of 528 rej09b0216-0300 bit bit name initial value r/w description 2 1 0 bc2 bc1 bc0 0 0 0 r/w r/w r/w bit counter 2 to 0 these bits specify the number of bits to be transferred next. when read, the remaining number of transfer bits is indicated. with the i 2 c bus format, the data is transferred with one addition acknowledge bit. bit bc2 to bc0 settings should be made during an interval between transfer frames. if bits bc2 to bc0 are set to a value other than 000, the setting should be made while the scl pin is low. the value returns to 000 at the end of a data transfer, including the acknowledge bit. with the clock synchronous serial format, these bits should not be modified. i 2 c bus format clock synchronous serial format 000: 9 bits 000: 8 bits 001: 2 bits 001: 1 bits 010: 3 bits 010: 2 bits 011: 4 bits 011: 3 bits 100: 5 bits 100: 4 bits 101: 6 bits 101: 5 bits 110: 7 bits 110: 6 bits 111: 8 bits 111: 7 bits 17.3.4 i 2 c bus interrupt enable register (icier) icier enables or disables interrupt sources and acknowledge bits, sets acknowledge bits to be transferred, and confirms acknowledge bits to be received. bit bit name initial value r/w description 7 tie 0 r/w transmit interrupt enable when the tdre bit in icsr is set to 1, this bit enables or disables the transmit data empty interrupt (txi). 0: transmit data empty interrupt request (txi) is disabled. 1: transmit data empty interrupt request (txi) is enabled.
section 17 i 2 c bus interface 2 (iic2) rev. 3.00 sep. 10, 2007 page 339 of 528 rej09b0216-0300 bit bit name initial value r/w description 6 teie 0 r/w transmit end interrupt enable this bit enables or disables the transmit end interrupt (tei) at the rising of the ninth clock while the tdre bit in icsr is 1. tei can be canceled by clearing the tend bit or the teie bit to 0. 0: transmit end interrupt request (tei) is disabled. 1: transmit end interrupt request (tei) is enabled. 5 rie 0 r/w receive interrupt enable this bit enables or disables the receive data full interrupt request (rxi) and the overrun error interrupt request (eri) with the clock synchronous format, when a receive data is transferred from icdrs to icdrr and the rdrf bit in icsr is set to 1. rxi can be canceled by clearing the rdrf or rie bit to 0. 0: receive data full interrupt request (rxi) and overrun error interrupt request (eri) with the clock synchronous format are disabled. 1: receive data full interrupt request (rxi) and overrun error interrupt request (eri) with the clock synchronous format are enabled. 4 nakie 0 r/w nack receive interrupt enable this bit enables or disables the nack receive interrupt request (naki) and the overrun error (setting of the ove bit in icsr) interrupt request (eri) with the clock synchronous format, when the nackf and al bits in icsr are set to 1. naki can be canceled by clearing the nackf, ove, or nakie bit to 0. 0: nack receive interrupt request (naki) is disabled. 1: nack receive interrupt request (naki) is enabled. 3 stie 0 r/w stop condition detection interrupt enable 0: stop condition detection interrupt request (stpi) is disabled. 1: stop condition detection interrupt request (stpi) is enabled.
section 17 i 2 c bus interface 2 (iic2) rev. 3.00 sep. 10, 2007 page 340 of 528 rej09b0216-0300 bit bit name initial value r/w description 2 acke 0 r/w acknowledge bit judgment select 0: the value of the receive acknowledge bit is ignored, and continuous transfer is performed. 1: if the receive acknowledge bit is 1, continuous transfer is halted. 1 ackbr 0 r receive acknowledge in transmit mode, this bit stores the acknowledge data that are returned by the receive device. this bit cannot be modified. 0: receive acknowledge = 0 1: receive acknowledge = 1 0 ackbt 0 r/w transmit acknowledge in receive mode, this bit specifies the bit to be sent at the acknowledge timing. 0: 0 is sent at the acknowledge timing. 1: 1 is sent at the acknowledge timing. 17.3.5 i 2 c bus status register (icsr) icsr performs confirmation of interrupt request flags and status. bit bit name initial value r/w description 7 tdre 0 r/w transmit data register empty [setting conditions] ? when data is transferred from icdrt to icdrs and icdrt becomes empty ? when trs is set ? when a start condition (including re-transfer) has been issued ? when transmit mode is entered from receive mode in slave mode [clearing conditions] ? when 0 is written in tdre after reading tdre = 1 ? when data is written to icdrt with an instruction
section 17 i 2 c bus interface 2 (iic2) rev. 3.00 sep. 10, 2007 page 341 of 528 rej09b0216-0300 bit bit name initial value r/w description 6 tend 0 r/w transmit end [setting conditions] ? when the ninth clock of scl rises with the i 2 c bus format while the tdre flag is 1 ? when the final bit of transmit frame is sent with the clock synchronous serial format [clearing conditions] ? when 0 is written in tend after reading tend = 1 ? when data is written to icdrt with an instruction 5 rdrf 0 r/w receive data register full [setting condition] ? when a receive data is transferred from icdrs to icdrr [clearing conditions] ? when 0 is written in rdrf after reading rdrf = 1 ? when icdrr is read with an instruction 4 nackf 0 r/w no acknowledge detection flag [setting condition] ? when no acknowledge is detected from the receive device in transmission while the acke bit in icier is 1 [clearing condition] ? when 0 is written in nackf after reading nackf = 1
section 17 i 2 c bus interface 2 (iic2) rev. 3.00 sep. 10, 2007 page 342 of 528 rej09b0216-0300 bit bit name initial value r/w description 3 stop 0 r/w stop condition detection flag [setting conditions] ? in master mode, when a stop condition is detected after frame transfer ? in slave mode, when a stop condition is detected after the following events: ? a general call is invoked ? a start condition is detected ? the first byte in the slave address matches the address set in the sar [clearing condition] ? when 0 is written in stop after reading stop = 1 2 al/ove 0 r/w arbitration lost flag/overrun error flag this flag indicates that arbitration was lost in master mode with the i 2 c bus format and that the final bit has been received while rdrf = 1 with the clock synchronous format. when two or more master devices attempt to seize the bus at nearly the same time, if the i 2 c bus interface detects data differing from the data it sent, it sets al to 1 to indicate that the bus has been taken by another master. [setting conditions] ? if the internal sda and sda pin disagree at the rise of scl in master transmit mode ? when the sda pin outputs high in master mode while a start condition is detected ? when the final bit is received with the clock synchronous format while rdrf = 1 [clearing condition] ? when 0 is written in al/ove after reading al/ove=1
section 17 i 2 c bus interface 2 (iic2) rev. 3.00 sep. 10, 2007 page 343 of 528 rej09b0216-0300 bit bit name initial value r/w description 1 aas 0 r/w slave address recognition flag in slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits sva6 to sva0 in sar. [setting conditions] ? when the slave address is detected in slave receive mode ? when the general call address is detected in slave receive mode. [clearing condition] ? when 0 is written in aas after reading aas=1 0 adz 0 r/w general call address recognition flag this bit is valid in i 2 c bus format slave receive mode. [setting condition] ? when the general call address is detected in slave receive mode [clearing condition] ? when 0 is written in adz after reading adz=1 17.3.6 slave address register (sar) sar selects the communication format and sets the sl ave address. when the ch ip is in slave mode with the i 2 c bus format, if the upper 7 bits of sar match the upper 7 bits of the first frame received after a start condition, the ch ip operates as the slave device. bit bit name initial value r/w description 7 to 1 sva6 to sva0 all 0 r/w slave address 6 to 0 these bits set a unique address in bits sva6 to sva0, differing form the addresses of other slave devices connected to the i 2 c bus. 0 fs 0 r/w format select 0: i 2 c bus format is selected. 1: clock synchronous serial format is selected.
section 17 i 2 c bus interface 2 (iic2) rev. 3.00 sep. 10, 2007 page 344 of 528 rej09b0216-0300 17.3.7 i 2 c bus transmit data register (icdrt) icdrt is an 8-bit readable/writable register that stores the transmit data. when icdrt detects the space in the shift register (icdrs ), it transfers the tr ansmit data which is written in icdrt to icdrs and starts transferring data. if the next transfer data is written to icdrt during transferring data of icdrs, continuous transfer is possible. if the mls bit of icmr is set to 1 and when the data is written to icdrt, the msb/lsb inverted data is read. the initial value of icdrt is h?ff. 17.3.8 i 2 c bus receive data register (icdrr) icdrr is an 8-bit register that stores the receive data. when data of one byte is received, icdrr transfers the receive data from icdrs to icdrr and the next data can be received. icdrr is a receive-only register, therefore the cpu cannot write to this register. th e initial value of icdrr is h?ff. 17.3.9 i 2 c bus shift register (icdrs) icdrs is a register that is used to transfer/recei ve data. in transmission, data is transferred from icdrt to icdrs and the data is sent from the s da pin. in reception, data is transferred from icdrs to icdrr after data of one byte is received. this register cannot be read directly from the cpu.
section 17 i 2 c bus interface 2 (iic2) rev. 3.00 sep. 10, 2007 page 345 of 528 rej09b0216-0300 17.4 operation the i 2 c bus interface can communicate either in i 2 c bus mode or clock synchronous serial mode by setting fs in sar. 17.4.1 i 2 c bus format figure 17.3 shows the i 2 c bus formats. figure 17.4 shows the i 2 c bus timing. the first frame following a start condition always consists of 8 bits. s sla r/ w a data a a/ a p 111 1 n 7 1 m (a) i 2 c bus format (fs = 0) (b) i 2 c bus format (start condition retransmission, fs = 0) n: transfer bit count (n = 1 to 8) m: transfer frame count (m 1) s sla r/ w a data 11 1 n1 7 1 m1 s sla r/ w a data a/ a p 11 1 n2 7 1 m2 1 1 1 a/ a n1 and n2: transfer bit count (n1 and n2 = 1 to 8) m1 and m2: transfer frame count (m1 and m2 1) 11 figure 17.3 i 2 c bus formats sda scl s 1-7 sla 8 r/ w 9 a 1-7 data 89 1-7 89 a data p a figure 17.4 i 2 c bus timing
section 17 i 2 c bus interface 2 (iic2) rev. 3.00 sep. 10, 2007 page 346 of 528 rej09b0216-0300 [legend] s: start condition. the master device drives sda from high to low while scl is high. sla: slave address r/ w : indicates the direction of data transfer: from the slave device to the master device when r/ w is 1, or from the master device to the slave device when r/ w is 0. a: acknowledge. the receive device drives sda to low. data: transfer data p: stop condition. the master device drives sda from low to high while scl is high. 17.4.2 master transmit operation in master transmit mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. for master transmit mode operation timing, refer to figures 17.5 and 17.6. the transmission procedur e and operations in master transmit mode are described below. 1. set the ice bit in iccr1 to 1. set the mls and wait bits in icmr and the cks3 to cks0 bits in iccr1 to 1. (initial setting) 2. read the bbsy flag in iccr2 to confirm that the bus is free. set the mst and trs bits in iccr1 to select master transmit mode. then, write 1 to bbsy and 0 to scp using mov instruction. (start condition issued) this generates the start condition. 3. after confirming that tdre in icsr has been set, write the transmit data (the first byte data show the slave address and r/ w ) to icdrt. at this time, tdre is automatically cleared to 0, and data is transferred from icdrt to icdrs. tdre is set again. 4. when transmission of one byte data is completed while tdre is 1, tend in icsr is set to 1 at the rise of the 9th transmit clock pulse. read the ackbr bit in icier, and confirm that the slave device has been selected. then, write seco nd byte data to icdrt. when ackbr is 1, the slave device has not been acknowledged, so issue the stop condition. to issue the stop condition, write 0 to bbsy and scp using mov instruction. scl is fixed low until the transmit data is prepared or the stop condition is issued. 5. the transmit data after the second byte is written to icdrt every time tdre is set. 6. write the number of bytes to be transmitted to icdrt. wait until tend is set (the end of last byte data transmission) while tdre is 1, or wait for nack (nackf in icsr = 1) from the receive device while acke in icier is 1. th en, issue the stop condition to clear tend or nackf. 7. when the stop bit in icsr is set to 1, the operation retu rns to the slave receive mode.
section 17 i 2 c bus interface 2 (iic2) rev. 3.00 sep. 10, 2007 page 347 of 528 rej09b0216-0300 tdre scl (master output) sda (master output) sda (slave output) tend [5] write data to icdrt (third byte) icdrt icdrs [2] instruction of start condition issuance [3] write data to icdrt (first byte) [4] write data to icdrt (second byte) user processing 1 bit 7 slave address address + r/ w data 1 data 1 data 2 address + r/ w bit 6 bit 7 bit 6 bit 5bit 4bit 3bit 2bit 1bit 0 212 3456789 a r/ w figure 17.5 master transmit mode operation timing (1) tdre [6] issue stop condition. clear tend. [7] set slave receive mode tend icdrt icdrs 1 9 23456789 a a/ a scl (master output) sda (master output) sda (slave output) bit 7 bit 6 data n data n bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 [5] write data to icdrt user processing figure 17.6 master transmit mode operation timing (2)
section 17 i 2 c bus interface 2 (iic2) rev. 3.00 sep. 10, 2007 page 348 of 528 rej09b0216-0300 17.4.3 master receive operation in master receive mode, the master device outputs the receive clock, receives data from the slave device, and returns an acknowledge signal. for ma ster receive mode operation timing, refer to figures 17.7 and 17.8. the reception procedure an d operations in master receive mode are shown below. 1. clear the tend bit in icsr to 0, then clear the trs bit in iccr1 to 0 to switch from master transmit mode to master receive mode . then, clear the tdre bit to 0. 2. when icdrr is read (dummy data read), recep tion is started, and the receive clock is output, and data received, in synchronization with the internal clock. the master device outputs the level specified by ackbt in icier to s da, at the 9th receive clock pulse. 3. after the reception of first frame data is completed, the rdrf bit in icst is set to 1 at the rise of 9th receive clock pulse. at this time, the r eceive data is read by reading icdrr, and rdrf is cleared to 0. 4. the continuous reception is performed by reading icdrr every time rdrf is set. if 8th receive clock pulse falls after reading icdrr by the other processing while rdrf is 1, scl is fixed low until icdrr is read. 5. if next frame is the last receive data, set th e rcvd bit in iccr1 to 1 before reading icdrr. this enables the issuance of the stop condition after the next reception. 6. when the rdrf bit is set to 1 at rise of the 9th receive clock pulse, issue the stage condition. 7. when the stop bit in icsr is set to 1, read icdrr. then clear the rcvd bit to 0. 8. the operation returns to the slave receive mode.
section 17 i 2 c bus interface 2 (iic2) rev. 3.00 sep. 10, 2007 page 349 of 528 rej09b0216-0300 tdre tend icdrs icdrr [1] clear tdre after clearing tend and trs [2] read icdrr (dummy read) [3] read icdrr 1 a 21 3456789 9 a trs rdrf scl (master output) sda (master output) sda (slave output) bit 7 master transmit mode master receive mode bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 user processing data 1 data 1 figure 17.7 master receive mode operation timing (1)
section 17 i 2 c bus interface 2 (iic2) rev. 3.00 sep. 10, 2007 page 350 of 528 rej09b0216-0300 rdrf rcvd icdrs icdrr data n-1 data n data n data n-1 [5] read icdrr after setting rcvd [6] issue stop condition [7] read icdrr, and clear rcvd [8] set slave receive mode 1 9 23456789 a a/ a scl (master output) sda (master output) sda (slave output) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 user processing figure 17.8 master receive mode operation timing (2) 17.4.4 slave transmit operation in slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signa l. for slave transmit mode operation timing, refer to figures 17.9 and 17.10. the transmission procedure and operations in slave transmit mode are described below. 1. set the ice bit in iccr1 to 1. set the mls and wait bits in icmr and the cks3 to cks0 bits in iccr1 to 1. (initial setting) set the mst and trs bits in iccr1 to select slave receive mode, and wait until the slave address matches. 2. when the slave address matches in the first frame following detection of the start condition, the slave device outputs the level specified by ackb t in icier to sda, at the rise of the 9th clock pulse. at this time, if the 8th bit data (r/ w ) is 1, the trs and icsr bits in iccr1 are set to 1, and the mode changes to slave transmit mode automatically. the continuous transmission is performed by writing transmit data to icdrt every time tdre is set. 3. if tdre is set after writing last transmit data to icdrt, wait until tend in icsr is set to 1, with tdre = 1. when tend is set, clear tend. 4. clear trs for the end processing, and read icdrr (dummy read). scl is free. 5. clear tdre.
section 17 i 2 c bus interface 2 (iic2) rev. 3.00 sep. 10, 2007 page 351 of 528 rej09b0216-0300 tdre tend icdrs icdrr 1 a 21 3456789 9 a trs icdrt scl (master output) slave receive mode slave transmit mode sda (master output) sda (slave output) scl (slave output) bit 7 bit 7 data 1 data 1 data 2 data 3 data 2 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 [2] write data to icdrt (data 1) [2] write data to icdrt (data 2) [2] write data to icdrt (data 3) user processing figure 17.9 slave transmit mode operation timing (1)
section 17 i 2 c bus interface 2 (iic2) rev. 3.00 sep. 10, 2007 page 352 of 528 rej09b0216-0300 tdre data n tend icdrs icdrr 1 9 2345678 9 trs icdrt a scl (master output) sda (master output) sda (slave output) scl (slave output) bit 7 slave transmit mode slave receive mode bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 a [3] clear tend [5] clear tdre [4] read icdrr (dummy read) after clearing trs user processing figure 17.10 slave transmit mode operation timing (2) 17.4.5 slave recei ve operation in slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. for slave receive mode operation timing, refer to figures 17.11 and 17.12. the reception procedur e and operations in slave receive mode are described below. 1. set the ice bit in iccr1 to 1. set the mls and wait bits in icmr and the cks3 to cks0 bits in iccr1 to 1. (initial setting) set the mst and trs bits in iccr1 to select slave receive mode, and wait until the slave address matches. 2. when the slave address matches in the first frame following detection of the start condition, the slave device outputs the level specified by ackb t in icier to sda, at the rise of the 9th clock pulse. at the same time, rdrf in icsr is set to read icdrr (dummy read). (since the read data show the slave address and r/ w , it is not used.)
section 17 i 2 c bus interface 2 (iic2) rev. 3.00 sep. 10, 2007 page 353 of 528 rej09b0216-0300 3. read icdrr every time rdrf is set. if 8th r eceive clock pulse falls while rdrf is 1, scl is fixed low until icdrr is read. the change of the acknowledge before reading icdrr, to be returned to the master device, is re flected to the next transmit frame. 4. the last byte data is read by reading icdrr. icdrs icdrr 12 1 345678 9 9 a a rdrf data 1 data 2 data 1 scl (master output) sda (master output) sda (slave output) scl (slave output) bit 7 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 [2] read icdrr (dummy read) [2] read icdrr user processing figure 17.11 slave receive mode operation timing (1) icdrs icdrr 12345678 9 9 a a rdrf scl (master output) sda (master output) sda (slave output) scl (slave output) user processing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 data 1 [3] set ackbt [3] read icdrr [4] read icdrr data 2 data 1 figure 17.12 slave receive mode operation timing (2)
section 17 i 2 c bus interface 2 (iic2) rev. 3.00 sep. 10, 2007 page 354 of 528 rej09b0216-0300 17.4.6 clock synchronous serial format this module can be operated with the clock s ynchronous serial format, by setting the fs bit in sar to 1. when the mst bit in iccr1 is 1, the transfer clock output from scl is selected. when mst is 0, the external clock input is selected. data transfer format figure 17.13 shows the clock synchronous serial transfer format. the transfer data is output from the rise to the fall of the scl clock, and the data at the rising edge of the scl clock is guaranteed. the mls bit in icmr sets the order of data transfer, in either the msb first or lsb first. the output level of sda can be changed during the transfer wait, by the sdao bit in iccr2. sda bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 scl figure 17.13 clock synchronous serial transfer format
section 17 i 2 c bus interface 2 (iic2) rev. 3.00 sep. 10, 2007 page 355 of 528 rej09b0216-0300 transmit operation in transmit mode, transmit data is output from sda, in synchronization with the fall of the transfer clock. the transfer clock is output when mst in iccr1 is 1, and is input when mst is 0. for transmit mode operation timing, refer to figure 17.14. the transmission procedure and operations in transmit mode are described below. 1. set the ice bit in iccr1 to 1. set the mst and cks3 to cks0 bits in iccr1 to 1. (initial setting) 2. set the trs bit in iccr1 to select the transmit mode. then, tdre in icsr is set. 3. confirm that tdre has been set. then, write the transmit data to icdrt. the data is transferred from icdrt to icdrs, and tdre is set automatically. the continuous transmission is performed by writing data to icdrt every time tdre is set. when changing from transmit mode to receive mode, clear trs while tdre is 1. 12 781 78 1 scl trs bit 0 data 1 data 1 data 2 data 3 data 2 data 3 bit 6 bit 7 bit 0 bit 6 bit 7 bit 0 bit 1 sda (output) tdre icdrt icdrs user processing [3] write data to icdrt [3] write data to icdrt [3] write data to icdrt [3] write data to icdrt [2] set trs figure 17.14 transmit mode operation timing
section 17 i 2 c bus interface 2 (iic2) rev. 3.00 sep. 10, 2007 page 356 of 528 rej09b0216-0300 receive operation in receive mode, data is latched at the rise of th e transfer clock. the tran sfer clock is output when mst in iccr1 is 1, and is i nput when mst is 0. for receive mode operation timing, refer to figure 17.15. the reception procedure and operati ons in receive mode are described below. 1. set the ice bit in iccr1 to 1. set the mst and cks3 to cks0 bits in iccr1 to 1. (initial setting) 2. when the transfer clock is output, set mst to 1 to start outputting the receive clock. 3. when the receive operation is completed, data is transferred from icdrs to icdrr and rdrf in icsr is set. when mst = 1, the next byte can be received, so the clock is continually output. the continuous reception is performed by reading icdrr every time rdrf is set. when the 8th clock is risen while rdrf is 1, the overrun is detected and al/ove in icsr is set. at this time, the pr evious reception data is retained in icdrr. 4. to stop receiving when mst = 1, set rcvd in iccr1 to 1, then read icdrr. then, scl is fixed high after receivi ng the next byte data. 12 781 7812 scl mst trs rdrf icdrs icdrr sda (input) bit 0 bit 6 bit 7 bit 0 bit 6 bit 7 bit 0 bit 1 bit 1 user processing data 1 data 1 data 2 data 2 data 3 [2] set mst (when outputting the clock) [3] read icdrr [3] read icdrr figure 17.15 receive mode operation timing
section 17 i 2 c bus interface 2 (iic2) rev. 3.00 sep. 10, 2007 page 357 of 528 rej09b0216-0300 17.4.7 noise filter the signal levels on the scl and sda pins are internally latched via the noise filter. figure 17.16 shows a block diagram of the noise filter circuit. the noise filter consists of two cascaded latche s and a match detector. the scl (or sda) input signal is sampled on the system clock. when both outputs of the latches match, its level is output to other blocks by the match detector. if they do not match, the previous value is held. c q d match detector internal scl or sda signal scl or sda input signal sampling clock sampling clock system clock cycle latch latch c q d figure 17.16 block diagram of noise filter 17.4.8 example of use flowcharts in respectiv e modes that use the i 2 c bus interface are shown in figures 17.17 to 17.20.
section 17 i 2 c bus interface 2 (iic2) rev. 3.00 sep. 10, 2007 page 358 of 528 rej09b0216-0300 bbsy=0 ? no tend=1 ? no yes start [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [13] [14] [15] initialize set mst and trs in iccr1 to 1. write 1 to bbsy and 0 to scp. write transmit data in icdrt write 0 to bbsy and scp set mst to 1 and trs to 0 in iccr1 read bbsy in iccr2 read tend in icsr read ackbr in icier mater receive mode yes ackbr=0 ? write transmit data in icdrt read tdre in icsr read tend in icsr clear tend in icsr read stop in icsr clear tdre in icsr end write transmit data in icdrt transmit mode? no yes tdre=1 ? last byte? stop=1 ? no no no no no yes yes tend=1 ? yes yes yes [1] test the status of the scl and sda lines. [2] set master transmit mode. [3] issue the start candition. [4] set the first byte (slave address + r/ w ) of transmit data. [5] wait for 1 byte to be transmitted. [6] test the acknowledge transferred from the specified slave device. [7] set the second and subsequent bytes (except for the final byte) of transmit data. [8] wait for icdrt empty. [9] set the last byte of transmit data. [10] wait for last byte to be transmitted. [11] clear the tend flag. [12] clear the stop flag. [13] issue the stop condition. [14] wait for the creation of stop condition. [15] set slave receive mode. clear tdre. [12] clear stop in icsr figure 17.17 sample flowchart for master transmit mode
section 17 i 2 c bus interface 2 (iic2) rev. 3.00 sep. 10, 2007 page 359 of 528 rej09b0216-0300 no yes rdrf=1 ? no yes rdrf=1 ? last receive - 1? mater receive mode clear tend in icsr clear trs in iccr1 to 0 clear tdre in icsr clear ackbt in icier to 0 dummy-read icdrr read rdrf in icsr read icdrr set ackbt in icier to 1 set rcvd in iccr1 to 1 read icdrr read rdrf in icsr write 0 to bbsy and scp read stop in icsr read icdrr clear rcvd in iccr1 to 0 clear mst in iccr1 to 0 note: do not activate an interrupt during the execution of steps [1] to [3]. supplementary explanation: when one byte is received, steps [2] to [6] are skipped after step [1], before jumping to step [7]. the step [8] is dummy-read in icdrr. end no yes stop=1 ? no yes [1] clear tend, select master receive mode, and then clear tdre. * [2] set acknowledge to the transmit device. * [3] dummy-read icddr. * [4] wait for 1 byte to be received [5] check whether it is the (last receive - 1). [6] read the receive data last. [7] set acknowledge of the final byte. disable continuous reception (rcvd = 1). [8] read the (final byte - 1) of receive data. [9] wait for the last byte to be receive. [10] clear the stop flag. [11] issue the stop condition. [12] wait for the creation of stop condition. [13] read the last byte of receive data. [14] clear rcvd. [15] set slave receive mode. [1] [2] [3] [4] [5] [6] [7] [8] [9] [11] [12] [13] clear stop in icsr. [10] [14] [15] figure 17.18 sample flowch art for master receive mode
section 17 i 2 c bus interface 2 (iic2) rev. 3.00 sep. 10, 2007 page 360 of 528 rej09b0216-0300 tdre=1 ? yes yes no slave transmit mode clear aas in icsr write transmit data in icdrt read tdre in icsr last byte? write transmit data in icdrt read tend in icsr clear tend in icsr clear trs in iccr1 to 0 dummy read icdrr clear tdre in icsr end [1] clear the aas flag. [2] set transmit data for icdrt (except for the last data). [3] wait for icdrt empty. [4] set the last byte of transmit data. [5] wait for the last byte to be transmitted. [6] clear the tend flag . [7] set slave receive mode. [8] dummy-read icdrr to release the scl line. [9] clear the tdre flag. no no yes tend=1 ? [1] [2] [3] [4] [5] [6] [7] [8] [9] figure 17.19 sample flowchart for slave transmit mode
section 17 i 2 c bus interface 2 (iic2) rev. 3.00 sep. 10, 2007 page 361 of 528 rej09b0216-0300 no yes rdrf=1 ? no yes rdrf=1 ? last receive - 1? slave receive mode clear aas in icsr clear ackbt in icier to 0 dummy-read icdrr read rdrf in icsr read icdrr set ackbt in icier to 1 read icdrr read rdrf in icsr read icdrr end no yes [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [1] clear the aas flag. [2] set acknowledge to the transmit device. [3] dummy-read icdrr. [4] wait for 1 byte to be received. [5] check whether it is the (last receive - 1). [6] read the receive data. [7] set acknowledge of the last byte. [8] read the (last byte - 1) of receive data. [9] wait the last byte to be received. [10] read for the last byte of receive data. supplementary explanation: when one byte is received, steps [2] to [6] are skipped after step [1], before jumping to step [7]. the step [8] is dummy-read in icdrr. figure 17.20 sample flowch art for slave receive mode
section 17 i 2 c bus interface 2 (iic2) rev. 3.00 sep. 10, 2007 page 362 of 528 rej09b0216-0300 17.5 interrupt request there are six interrupt requests in this module; tran smit data empty, transmit end, receive data full, nack receive, stop recognition, and arbitrati on lost/overrun error. table 17.3 shows the contents of each interrupt request. table 17.3 interrupt requests interrupt request abbreviat ion interrupt condition i 2 c mode clock synchronous mode transmit data empty txi (tdre=1) ? (tie=1) { { transmit end tei (tend=1) ? (teie=1) { { receive data full rxi (rdrf=1) ? (rie=1) { { stop recognition stpi (stop=1) ? (stie=1) { nack receive { arbitration lost/overrun error naki {(nackf=1)+(al=1)} ? (nakie=1) { { when interrupt conditions described in table 17.3 are 1 and the i bit in ccr is 0, the cpu executes an interrupt exception processing. interrupt sources should be cleared in the exception processing. tdre and tend are automatically cleared to 0 by writing the transmit data to icdrt. rdrf are automatically cleared to 0 by r eading icdrr. tdre is set to 1 again at the same time when transmit data is written to icdrt. when tdre is cleared to 0, then an excessive data of one byte may be transmitted.
section 17 i 2 c bus interface 2 (iic2) rev. 3.00 sep. 10, 2007 page 363 of 528 rej09b0216-0300 17.6 bit synchronous circuit in master mode, this module has a possibility that high level period may be short in the two states described below. ? when scl is driven to low by the slave device ? when the rising speed of scl is lowered by the load of the scl line (l oad capacitance or pull- up resistance) therefore, it monitors scl and communicates by bit with synchronization. figure 17.21 shows the timing of the bit synchronous circuit and table 17.4 shows the time when scl output changes from low to hi-z then scl is monitored. scl vih scl monitor timing reference clock internal scl figure 17.21 the timing of the bit synchronous circuit table 17.4 time for monitoring scl cks3 cks2 time for monitoring scl 0 7.5 tcyc 0 1 19.5 tcyc 0 17.5 tcyc 1 1 41.5 tcyc
section 17 i 2 c bus interface 2 (iic2) rev. 3.00 sep. 10, 2007 page 364 of 528 rej09b0216-0300 17.7 usage notes 17.7.1 issue (retransmission) of start/stop conditions in master mode, when the start/stop conditions are issued (retransmitted) at the specific timing under the following condition 1 or 2, such cond itions may not be output successfully. to avoid this, issue (retransmit) the start/stop conditions after the fall of the ninth clock is confirmed. check the sclo bit in the i 2 c control register 2 (iicr2) to confirm the fall of the ninth clock. 1. when the rising of scl falls behind the time specified in section 17.6, bit synchronous circuit, by the load of the scl bus (load capacitance or pull-up resistance) 2. when the bit synchronous circuit is activated by extending the low period of eighth and ninth clocks, that is driven by the slave device 17.7.2 wait setting in i 2 c bus mode register (icmr) if the wait bit is set to 1, and the scl signal is driven low for two or more transfer clocks by the slave device at the eighth and ninth clocks, the high period of ninth clock may be shortened. to avoid this, set the wait bit in icmr to 0.
section 17 i 2 c bus interface 2 (iic2) rev. 3.00 sep. 10, 2007 page 365 of 528 rej09b0216-0300 17.7.3 restriction in use of multi-master (1) restriction on setting transfer rate in multi-master usage when i 2 c transfer rate setting of this lsi is lower than those of the other masters, unexpected length of scl may occasionally be output. to avoid this, the specified value must be greater than or equal to the value pro duced by multiplying the fast est transfer rate among the other masters by 1/1.8. for example, when the transfer rate of the fastest bus master among the other bus masters is 400 kbps, the transfer rate of the i 2 c of this lsi must be set to at least 223 kbps (= 400/1.8). (2) restriction on use of bit manipulation instructions to set mst and trs when master transmission is selected by cons ecutively manipulating the mst and trs bits in multi-master usage, an arbitration loss during execution of the bit-manipulation instruction for trs leads to the contradictory s ituation where al in icsr is 1 in master transmit mode (mst = 1, trs = 1). ways to avoid this effect are listed below. ? use the mov instruction to set mst and trs in multi-master usage. ? when arbitration is lost, confirm that mst = 0 and trs = 0. if the setting of mst = 0 and trs = 0 is not confirmed, set mst = 0 and trs = 0 again. 17.7.4 continuous data recepti on in master receive mode in master receive mode, when scl is fixed low on the falling edge of the 8th clock while the rdrf bit is set to 1 and icdrr is read around the falling edge of the 8th clock, the clock is only fixed low in the 8th clock of the next round of data reception. the scl is then released from its fixed state without reading icdrr and the 9th clock is output. as a result, some receive data is lost. ways to avoid this phenomenon are listed below. ? read icdrr in master receive mode befo re the rising edge of the 8th clock. ? set rcvd to 1 in master receive mode and perform communication in units of one byte.
section 17 i 2 c bus interface 2 (iic2) rev. 3.00 sep. 10, 2007 page 366 of 528 rej09b0216-0300
section 18 a/d converter adcms32a_000020020200 rev. 3.00 sep. 10, 2007 page 367 of 528 rej09b0216-0300 section 18 a/d converter this lsi includes a successive approximation type 10-bit a/d converter that allows up to eight analog input channels to be selected. the block diagram of the a/d converter is shown in figure 18.1. 18.1 features ? 10-bit resolution ? eight input channels ? conversion time: at least 3.5 s per channel (at 20-mhz operation) ? two operating modes ? single mode: single-channel a/d conversion ? scan mode: continuous a/d conversion on 1 to 4 channels ? four data registers ? conversion results are held in a data register for each channel ? sample-and-hold function ? two conversion start methods ? software ? external trigger signal ? interrupt request ? an a/d conversion end interrupt request (adi) can be generated
section 18 a/d converter rev. 3.00 sep. 10, 2007 page 368 of 528 rej09b0216-0300 module data bus control circuit internal data bus 10-bit d/a comparator + sample-and- hold circuit adi interrupt bus interface successive approximations register analog multiplexer a d c s r a d c r a d d r d a d d r c a d d r b a d d r a an0 an1 an2 an3 an4 an5 an6 an7 a/d control register a/d control/status register a/d data register a a/d data register b a/d data register c a/d data register d [legend] adcr: adcsr: addra: addrb: addrc: addrd: adtrg av cc figure 18.1 block diagram of a/d converter
section 18 a/d converter rev. 3.00 sep. 10, 2007 page 369 of 528 rej09b0216-0300 18.2 input/output pins table 18.1 summarizes the input pins used by the a/d converter. the 8 analog input pins are divided into two groups; analog input pins 0 to 3 (an0 to an3) comprising group 0, analog input pins 4 to 7 (an4 to an7) comprising group 1. the avcc pin is the power supply pin for the analog block in the a/d converter. table 18.1 pin configuration pin name abbreviation i/o function analog power supply pin av cc input analog block power supply analog input pin 0 an0 input analog input pin 1 an1 input analog input pin 2 an2 input analog input pin 3 an3 input group 0 analog input analog input pin 4 an4 input analog input pin 5 an5 input analog input pin 6 an6 input analog input pin 7 an7 input group 1 analog input a/d external trigger input pin adtrg input external trigger input for starting a/d conversion
section 18 a/d converter rev. 3.00 sep. 10, 2007 page 370 of 528 rej09b0216-0300 18.3 register descriptions the a/d converter has the following registers. ? a/d data register a (addra) ? a/d data register b (addrb) ? a/d data register c (addrc) ? a/d data register d (addrd) ? a/d control/status register (adcsr) ? a/d control register (adcr) 18.3.1 a/d data registers a to d (addra to addrd) there are four 16-bit read-only addr registers; addra to addrd, used to store the results of a/d conversion. the addr registers, which store a conversion result for each analog input channel, are shown in table 18.2. the converted 10-bit data is stored in bits 15 to 6. the lower 6 bits are always read as 0. the data bus width between the cpu and the a/d converter is 8 bits. the upper byte can be read directly from the cpu, however the lower byte should be read via a temporary register. the temporary register contents are transferred from the addr when the upper byte data is read. when reading addr, read the upper byte first then the lower one, or read in word units. the addr is initialized to h'0000. table 18.2 analog input channels and corresponding addr registers analog input channel group 0 group 1 a/d data register to be stored results of a/d conversion an0 an4 addra an1 an5 addrb an2 an6 addrc an3 an7 addrd
section 18 a/d converter rev. 3.00 sep. 10, 2007 page 371 of 528 rej09b0216-0300 18.3.2 a/d control/status register (adcsr) adcsr consists of the control bits and conversion end status bits of the a/d converter. bit bit name initial value r/w description 7 adf 0 r/w a/d end flag [setting conditions] ? when a/d conversion ends in single mode ? when a/d conversion ends once on all the channels selected in scan mode [clearing condition] ? when 0 is written after reading adf = 1 6 adie 0 r/w a/d interrupt enable a/d conversion end interrupt request (adi) is enabled by adf when this bit is set to 1 5 adst 0 r/w a/d start setting this bit to 1 starts a/d conversion. in single mode, this bit is cleared to 0 automatically when conversion on the specified channel is complete. in scan mode, conversion continues sequentially on the specified channels until this bit is cleared to 0 by software, a reset, or a transition to standby mode. 4 scan 0 r/w scan mode selects single mode or scan mode as the a/d conversion operating mode. 0: single mode 1: scan mode 3 cks 0 r/w clock select selects the a/d conversions time. 0: conversion time = 134 states (max.) 1: conversion time = 70 states (max.) clear the adst bit to 0 before switching the conversion time.
section 18 a/d converter rev. 3.00 sep. 10, 2007 page 372 of 528 rej09b0216-0300 bit bit name initial value r/w description 2 1 0 ch2 ch1 ch0 0 0 0 r/w r/w r/w channel select 2 to 0 select analog input channels. when scan = 0 when scan = 1 000: an0 000: an0 001: an1 001: an0 and an1 010: an2 010: an0 to an2 011: an3 011: an0 to an3 100: an4 100: an4 101: an5 101: an4 and an5 110: an6 110: an4 to an6 111: an7 111: an4 to an7 18.3.3 a/d control register (adcr) adcr enables a/d conversion started by an external trigger signal. bit bit name initial value r/w description 7 trge 0 r/w trigger enable a/d conversion is started at the falling edge and the rising edge of the external trigger signal ( adtrg ) when this bit is set to 1. the selection between the falling edge and rising edge of the external trigger pin ( adtrg ) conforms to the wpeg5 bit in the interrupt edge select register 2 (iegr2) 6 to 1 ? all 1 ? reserved these bits are always read as 1. 0 ? 0 r/w reserved do not set this bit to 1, though the bit is readable/writable.
section 18 a/d converter rev. 3.00 sep. 10, 2007 page 373 of 528 rej09b0216-0300 18.4 operation the a/d converter operates by successive appr oximation with 10-bit resolution. it has two operating modes; single mode and scan mode. when changing the operating mode or analog input channel, in order to prevent incorrect operation, first clear the bit adst in adcsr to 0. the adst bit can be set at the same time as the opera ting mode or analog input channel is changed. 18.4.1 single mode in single mode, a/d conversion is performed once for the analog input of the specified single channel as follows: 1. a/d conversion is started when the adst bit in adcsr is set to 1, according to software or external trigger input. 2. when a/d conversion is completed, the result is transferred to the corresponding a/d data register of the channel. 3. on completion of conversion, the adf bit in adcsr is set to 1. if the adie bit is set to 1 at this time, an adi interrupt request is generated. 4. the adst bit remains set to 1 during a/d conversion. when a/d conversion ends, the adst bit is automatically cleared to 0 and the a/d converter enters the wait state. 18.4.2 scan mode in scan mode, a/d conversion is performed sequentially for the analog input of the specified channels (four channels maximum) as follows: 1. when the adst bit in adcsr is set to 1 by software or external trigger input, a/d conversion starts on the first channel in the group (an0 when ch2 = 0, an4 when ch2 = 1). 2. when a/d conversion for each channel is completed, the result is sequentially transferred to the a/d data register corresponding to each channel. 3. when conversion of all the selected channels is completed, the adf flag in adcsr is set to 1. if the adie bit is set to 1 at this time, an adi interrupt requested is generated. a/d conversion starts again on the first channel in the group. 4. the adst bit is not automatically cleared to 0. steps [2] and [3] are repeated as long as the adst bit remains set to 1. when the adst bit is cleared to 0, a/d conversion stops.
section 18 a/d converter rev. 3.00 sep. 10, 2007 page 374 of 528 rej09b0216-0300 18.4.3 input sampling and a/d conversion time the a/d converter has a built-in sample-and-hold circuit. the a/d converter samples the analog input when the a/d conversion start delay time (t d ) has passed after the adst bit is set to 1, then starts conversion. figure 18.2 shows the a/d conversion timing. table 18.3 shows the a/d conversion time. as indicated in figure 18.2, the a/d conversion time includes t d and the input sampling time. the length of t d varies depending on the timing of the write access to adcsr. the total conversion time therefore varies within the ranges indicated in table 18.3. in scan mode, the values given in table 18.3 apply to the first conversion time. in the second and subsequent conversions, the conversion time is 128 states (fixed) when cks = 0 and 66 states (fixed) when cks = 1. (1) (2) t d t spl t conv address write signal input sampling timing adf [legend] (1): (2): t d : t spl : t conv : adcsr write cycle adcsr address a/d conversion start delay time input sampling time a/d conversion time figure 18.2 a/d conversion timing
section 18 a/d converter rev. 3.00 sep. 10, 2007 page 375 of 528 rej09b0216-0300 table 18.3 a/d conversion time (single mode) cks = 0 cks = 1 item symbol min. typ. max. min. typ. max. a/d conversion start delay time t d 6 ? 9 4 ? 5 input sampling time t spl ? 31 ? ? 15 ? a/d conversion time t conv 131 ? 134 69 ? 70 note: all values represent the number of states. 18.4.4 external trigger input timing a/d conversion can also be started by an external trigger input. when the trge bit in adcr is set to 1, external trigger input is enabled at the adtrg pin. a falling edge at the adtrg input pin sets the adst bit in adcsr to 1, starting a/d conversion. other operations, in both single and scan modes, are the same as when the bit adst has been set to 1 by software. figure 18.3 shows the timing. adtrg internal trigger signal adst a/d conversion figure 18.3 external trigger input timing
section 18 a/d converter rev. 3.00 sep. 10, 2007 page 376 of 528 rej09b0216-0300 18.5 a/d conversion accu racy definitions this lsi's a/d conversion accuracy definitions are given below. ? resolution the number of a/d converter digital output codes ? quantization error the deviation inherent in the a/d converter, given by 1/2 lsb (see figure 18.4). ? offset error the deviation of the analog input voltage value from the ideal a/d conversion characteristic when the digital output changes from the minimum voltage value 0000000000 to 0000000001 (see figure 18.5). ? full-scale error the deviation of the analog input voltage value from the ideal a/d conversion characteristic when the digital output changes from 1111111110 to 1111111111 (see figure 18.5). ? nonlinearity error the deviation from the ideal a/d conversion characteristic as the voltage changes from zero to full scale. this does not include the offset er ror, full-scale error, or quantization error. ? absolute accuracy the deviation between the digital value and the analog input value. includes offset error, full- scale error, quantization erro r, and nonlinearity error.
section 18 a/d converter rev. 3.00 sep. 10, 2007 page 377 of 528 rej09b0216-0300 111 110 101 100 011 010 001 000 1 8 2 8 6 8 7 8 fs quantization error digital output ideal a/d conversion characteristic analog input voltage 3 8 4 8 5 8 figure 18.4 a/d conversion accuracy definitions (1) fs digital output ideal a/d conversion characteristic nonlinearity error analog input voltage offset error actual a/d conversion characteristic full-scale error figure 18.5 a/d conversion accuracy definitions (2)
section 18 a/d converter rev. 3.00 sep. 10, 2007 page 378 of 528 rej09b0216-0300 18.6 usage notes 18.6.1 permissible sign al source impedance this lsi's analog input is designed such that conversion accuracy is guaranteed for an input signal for which the signal source impedance is 5 k ? or less. this specification is provided to enable the a/d converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 5 k ? , charging may be insufficient and it may not be possible to guarantee a/d conversion accuracy. howe ver, for a/d conversion in single mode with a large capacitance provided externa lly, the input load will essentia lly comprise only the internal input resistance of 10 k ? , and the signal source impedance is ignored. however, as a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mv/ s or greater) (see figure 18.6). when converting a high-speed analog signal or converting in scan mode, a low-impedance buffer should be inserted. 18.6.2 influences on absolute accuracy adding capacitance results in coupling with gnd, and therefore noise in gnd may adversely affect absolute accuracy. be su re to make the connection to an electrically stable gnd. care is also required to ensure that filter circuits do not interfere with digital signals or act as antennas on the mounting board. 20 pf 10 k ? c in = 15 pf sensor output impedance up to 5 k ? this lsi low-pass filter c to 0.1 f sensor input a/d converter equivalent circuit figure 18.6 analog input circuit example
section 19 band-gap circuit, power-on reset, and low-voltage detection circuits lvi0000a_000020030300 rev. 3.00 sep. 10, 2007 page 379 of 528 rej09b0216-0300 section 19 band-gap circuit, power-on reset, and low-voltage detection circuits this lsi can include a band-gap circuit (bgr, band-gap regulator), a power-on reset circuit and low-voltage detection circuit. bgr supplies a reference voltage to the on-chip oscillator and low-voltage detection circuit. figure 19.1 shows the block diagram of how bgr is allocated. the low-voltage detection (lvd) circuit consists of two circuits: lvdi (interrupt by low voltage detection) and lvdr (reset by low voltage detection) circuits. this circuit is used to prevent abnormal operation (program runaway) from occurring due to the power supply voltage fall and to recreate the state before the power supply voltage fall when the power supply voltage rises again. even if the power supply voltage falls, the unstable state when the power supply voltage falls below the guaranteed operating voltage can be removed by entering standby mode when exceeding the guaranteed operating voltage and during normal operation. thus, system stability can be improved. if the power supply voltage falls more, the reset state is automatically entered. if the power supply voltage rises again, the reset stat e is held for a specified period, then active mode is automatically entered. figure 19.2 is a block diagram of the power-on reset circuit and the low-voltage detection circuit.
section 19 band-gap circuit, power-on reset, and low-voltage detection circuits rev. 3.00 sep. 10, 2007 page 380 of 528 rej09b0216-0300 19.1 features ? bgr circuit supplies stable reference voltage covering the entire operating voltage range and the operating temperature range. ? power-on reset circuit uses an external capacitor to ge nerate an internal reset signal when power is first supplied. ? low-voltage detection circuit lvdr: monitors the power-supply voltage, and generates an internal reset signal when the voltage falls below a given value. lvdi: monitors the power-supply voltage, and generates an interrupt when the voltage falls below or rises above respective given values. two detection levels for reset generation voltage are available: when only the lvdr circuit is used, or when the lvdi and lvdr circuits are both used. ? reset source decision the source of a reset can be decided by reading the reset source decision register in the reset exception handler. [legend] vcc: power supply vcl: internal power supply generated from vcc by the step-down circuit vbgr: reference voltage from bgr vclsel: select signal for the source of the on-chip oscillator power supply rcstp: on-chip oscillator stop signal step-down circuit on-chip oscillator lvd (low-voltage detection circuit) vcc vcl vbgr vclsel rcstp bgr figure 19.1 block diagram around bgr
section 19 band-gap circuit, power-on reset, and low-voltage detection circuits rev. 3.00 sep. 10, 2007 page 381 of 528 rej09b0216-0300 res cres ck r pss vbgr extu extd vddii vcc r s q ovf vreset vintd vintu lvdres lvdcr lvdsr lvdint [legend] pss: prescaler s lvdcr: low-voltage-detection control register lvdsr: low-voltage-detection status register vbgr: reference voltage from bgr extd: compared voltage for falling external input voltage extu: compared voltage for rising external input voltage vddii: bit 5 in lvdcr noise filter circuit noise filter circuit internal reset signal power-on reset circuit interrupt control circuit internal data bus interrupt request ladder network external power supply 150 k ? figure 19.2 block diagram of power-on reset circuit and low-voltage detection circuit
section 19 band-gap circuit, power-on reset, and low-voltage detection circuits rev. 3.00 sep. 10, 2007 page 382 of 528 rej09b0216-0300 19.2 register descriptions the low-voltage detection circuit has the following registers. ? low-voltage-detection control register (lvdcr) ? low-voltage-detection status register (lvdsr) ? reset source decision register (lvdrf) 19.2.1 low-voltage-detection control register (lvdcr) lvdcr selects the compared voltage of the lvdi circuit, sets the detection levels for the lvdr circuit, enables or disables the lvdr circuit, and enables or disables generation of an interrupt when the power-supply voltage rises above or falls below the respective levels. table 19.1 shows the relationship between the lvdcr settings and functions to be selected. lvdcr should be set according to table 19.1. bit bit name initial value r/w description 7, 6 ? all 1 ? reserved these bits are always read as 1 and cannot be modified. 5 vddii 1 * 1 r/w lvdr external compared voltage input inhibit 0: use external voltage as lvdi compared voltage 1: use internal voltage as lvdi compared voltage 4 ? 1 ? reserved this bit is always read as 1 and cannot be modified. 3 lvdsel * 2 1 r/w lvdr detection level select 0: reset detection voltage is 2.3 v (typ.) 1: reset detection voltage is 3.6 v (typ.) when the falling or rising voltage detection interrupt is used, the reset detection voltage of 2.3 v (typ.) should be used. when only a reset detection interrupt is used, reset detection voltage of 3.6 v (typ.) should be used. 2 ? 1 ? reserved this bit is always read as 1 and cannot be modified.
section 19 band-gap circuit, power-on reset, and low-voltage detection circuits rev. 3.00 sep. 10, 2007 page 383 of 528 rej09b0216-0300 bit bit name initial value r/w description 1 lvdde 0 r/w voltage-fall-interrupt enable 0: interrupt on the power-supply voltage falling disabled 1: interrupt on the power-supply voltage falling enabled 0 lvdue 0 r/w voltage-rise-interrupt enable 0: interrupt on the power-supply voltage rising disabled 1: interrupt on the power-supply voltage rising enabled notes: 1. not initialized by an lvdr but initialized by a power-on reset or a watchdog timer reset. 2. for 3.3-v-specification models, this bit 3 of this register is a reserved bit (initial value is 0) and the reset detection voltage is 2.3 v (typ.). table 19.1 lvdcr settings and select functions lvdcr settings select functions vddii lvdsel lvdde lvdue power-on reset lvdr low-voltage- detection fall interrupt low-voltage- detection rise interrupt * 1 0 0 ? ? * 0 1 0 ? * 0 1 1 note: * set these bits if necessary.
section 19 band-gap circuit, power-on reset, and low-voltage detection circuits rev. 3.00 sep. 10, 2007 page 384 of 528 rej09b0216-0300 19.2.2 low-voltage-detection status register (lvdsr) lvdsr indicates whether the power-supply voltage falls below or rises above the respective given values. bit bit name initial value r/w description 7 to 2 ? all 1 ? reserved these bits are always read as 1 and cannot be modified. 1 lvddf 0 * r/w lvd power-supply voltage fall flag [setting condition] ? when the power-supply voltage falls below vint (d) (typ. = 3.7 v) [clearing condition] ? when writing 0 to this bit after reading it as 1 0 lvduf 0 * r/w lvd power-supply voltage rise flag [setting condition] ? when the power supply voltage falls below vint (d) while the lvdue bit in lvdcr is set to 1 and then rises above vint (u) (typ. = 4.0 v) before falling below vreset1 (typ. = 2.3 v) [clearing condition] ? when writing 0 to this bit after reading it as 1 note: * initialized by an lvdr.
section 19 band-gap circuit, power-on reset, and low-voltage detection circuits rev. 3.00 sep. 10, 2007 page 385 of 528 rej09b0216-0300 19.2.3 reset source decision register (lvdrf) lvdsr indicates sources of resets. bit bit name initial value r/w description 7 to 2 ? ? ? reserved the read value is undefined and these bits cannot be modified. 1 prst * 1 r/w por/lvdr detection [setting conditions] ? when a power-on reset has occurred ? when an lvdr has occurred [clearing condition] when writing 0 0 wrst * 2 r/w wdt reset detection [setting condition] ? when a reset by the wdt has occurred [clearing conditions] ? when a power-on reset has occurred ? when an lvdr has occurred ? when an reset signal input on the external pin has asserted ? when writing 0 notes: 1. the initial value depends on the condition when the prst bit is set or cleared. 2. the initial value depends on the condition when the wrst bit is set or cleared.
section 19 band-gap circuit, power-on reset, and low-voltage detection circuits rev. 3.00 sep. 10, 2007 page 386 of 528 rej09b0216-0300 19.3 operations 19.3.1 power-on reset circuit figure 19.3 shows the timing of the operation of the power-on reset circuit. as the power-supply voltage rises, the capacitor which is externally connected to the res pin is gradually charged via the internal pull-up resistor (typ. 150 k ? ). while the res signal is driven low, the prescaler s and the entire chip retains the reset state. when the level on the res signal reaches the specified value, the prescaler s is released from its reset state a nd it starts counting. the ovf signal is generated to release the internal reset signal after the prescaler s has counted 131,072 cycles of the clock. the noise filter circuit which removes noise with less than 400 ns (typ.) is in cluded to prevent the incorrect operation of this lsi caused by noise on the res signal. to achieve stable operation of this lsi, the power supply needs to rise to its full level and settles within the specified time. the maximum time required for the power supply to rise and settle (t pwon ) is determined by the oscillation frequency (f osc ) and capacitance whic h is connected to res pin (c res ). where t pwon is assumed to be the time required to reach 90 % of the full level of the power supply, the power supply circuit should be designed to satisfy the following formula. t pwon (ms) 90 c res ( f) + 162/f osc (mhz) (t pwon 3000 ms, c res 0.22 f, and f osc = 10 in 2-mhz to 10-mhz operation) note that the power supply voltage (vcc) must fall below vpor = 100 mv to remove charge on the res pin. after that, it can be risen. to remove charge on the res pin, it is recommended that the diode should be placed to vcc. if the power supp ly voltage (vcc) rises from the point above vpor, a power-on reset may not occur.
section 19 band-gap circuit, power-on reset, and low-voltage detection circuits rev. 3.00 sep. 10, 2007 page 387 of 528 rej09b0216-0300 res vcc pss-reset signal internal reset signal vss vss ovf 131,072 cycles pss counter starts reset released t pwon vpor figure 19.3 operational timing of power-on reset circuit 19.3.2 low-voltage detection circuit lvdr (reset by low voltage detection) circuit: figure 19.4 shows the timing of the operation of the lvdr circuit. the lvdr circuit is kept enabled during the lsi's operation. when the power-supply voltage falls below the vreset voltage (the value selected by the lvdsel bit: typ. = 2.3 v or 3.6 v), the lvdr circuit clears the lvdres signal to 0, and resets prescaler s. the low-voltage detection reset state remains in place until a power-on reset is generated. when the power-supply voltage rises above the vreset voltage (typ. = 3.6 v) regardless of lvdsel bit setting) again, the lvdr circuit sets the lvdres signal to 1 and prescaler s starts counting. when 131,072 clock ( ) cycles have been counted, the internal reset signal is released. in this case, the lvdsel bit in lvdcr is initialized (the vreset voltage: typ. = 3.6 v) though the vddii bit is not initialized. if the power supply voltage (vcc) falls below vpor = 100 mv, a power-on reset occurs.
section 19 band-gap circuit, power-on reset, and low-voltage detection circuits rev. 3.00 sep. 10, 2007 page 388 of 528 rej09b0216-0300 lvdres v cc vreset v ss v lvdrmin ovf pss-reset signal internal reset signal 131,072 cycles pss counter starts reset released figure 19.4 operating timing of lvdr circuit
section 19 band-gap circuit, power-on reset, and low-voltage detection circuits rev. 3.00 sep. 10, 2007 page 389 of 528 rej09b0216-0300 low voltage detection interrupt (lvdi) circuit (when internally gen erated voltage is used for detection): figure 19.5 shows the timing of the operation of the lvdi circuit. the lvdi circuit is enabled after a power-on reset, however, the interrupt request is disabled. to enable the lvdi, the lvddf bit and lvduf bit in lvdsr must be cleared to 0 and then the lvdde bit or lvdue bit in lvdcr must be set to 1. after that, the output settings of ports must be made. when the power-supply voltage falls below vint (d) (typ. = 3.7 v) voltage, the lvdi circuit clears the lvdint signal to 0 and sets the lvddf bit to 1. if the lvdde bit is 1 at this time, an irq0 interrupt request is generated. in this case, the necessary data must be saved in the external eeprom and a transition to standby mode or subsl eep mode must be made. until this processing is completed, the power supply voltage must be higher than the lower limit of the guaranteed operating voltage. when the power-supply voltage does not fall below the vreset1 (typ. = 2.3 v) voltage and rises above the vint (u) (typ. = 4.0 v) voltage, the lvdi circuit sets the lvdint signal to 1. if the lvdue bit is 1 at this time, the lvduf bit in lvds r is set to 1 and an irq0 interrupt request is simultaneously generated. if the power supply voltage (vcc) falls below the vreset1 (typ. = 2.3 v) voltage, this lsi enters low voltage detection reset operation (when lvdre = 1). lvdint vcc vint (d) vint (u) vss lvddf lvdue lvduf irq0 interrupt generated irq0 interrupt generated lvdde vreset1 figure 19.5 operational timing of lvdi circuit
section 19 band-gap circuit, power-on reset, and low-voltage detection circuits rev. 3.00 sep. 10, 2007 page 390 of 528 rej09b0216-0300 low voltage detection interrupt (lvdi) circuit (when voltages input via extu and extd pins are used for detection): figure 19.6 shows the timing of the lvdi circuit. the lvdi circuit is enabled after a power-on reset, however, the interrupt request is disabled. to enable the lvdi, the lvddf and lvduf bits in lvdsr must be cleared to 0 and the lvdde or lvdue bit in lvdcr must be set to 1. when using external compared voltage, write 0 to the vddii bit in lvdcr, and wait for 50 s (t lvdon ) given by a software timer until the detection circuit has settled. then clear the lvddf and lvduf bits to 0 and set the lvdde or lvdue bit to 1. after that, the output settings of ports must be made. the initial value of the external compared voltages input on the extu and extd pins must be higher than the vexd voltage. when the external comparison voltage of extd pin falls below the vexd (d) (typ. = 1.15 v) voltage, the lvdi clears the lvdint signal to 0 and sets the lvddf bit in lvdsr to 1. if the lvdde bit is 1 at this tim e, an irq0 interrupt request is gene rated. in this case, the necessary data must be saved in the external eeprom, and a transition to standby mode or subsleep mode must be made. until this processing is completed, the power supply voltage must be higher than the lower limit of the guaranteed operating voltage. when the power-supply voltage does not fall below the vreset1 (typ. = 2.3 v) voltage and the input voltage of the extu pin rises above vexd (typ. = 1.15 v) voltage, the lvdi circuit sets the lvdint signal to 1. if the lvdue bit is 1 at this time, the lvduf bit in lvdsr is set to 1 and an irq0 interrupt request is generated. if the power supply voltage falls below the vreset1 (typ. = 2.3 v) voltage, this lsi enters low- voltage detection reset operation. when the voltages input on the extu and extd pins are used as the compared voltage, ensure to use the lvdr (reset detection voltage: typ. = 2.3 v) circuit.
section 19 band-gap circuit, power-on reset, and low-voltage detection circuits rev. 3.00 sep. 10, 2007 page 391 of 528 rej09b0216-0300 lvdint vexd v ss v reset1 lvddf lvdue lvduf lvdde (1) (2) (3) (4) irq0 interrupt generated external power supply voltage extd input voltage extu input voltage irq0 interrupt generated figure 19.6 operational timing of lvdi circuit (when compared voltage is input through extu and extd pins)
section 19 band-gap circuit, power-on reset, and low-voltage detection circuits rev. 3.00 sep. 10, 2007 page 392 of 528 rej09b0216-0300 19.3.3 deciding reset source the source of a reset can be decided by reading th e reset source decision register (lvdrf) in the reset exception handler (see table 19.2). after that, wr iting 0 to the bit can clea r the flag and can be ready to decide the next reset source. figure 19.7 shows a timing of setting the bits in the register. table 19.2 deciding reset source lvdrf prst wrst reset source 1 0 power-on reset or lvdr occurred 0 0 reset signal input on external reset pin 0 1 wdt reset occurred wrst bit set by power-on reset read and cleared (0 is written) prst bit internal reset signal power supply voltage set by temporary drop of power supply voltage read and cleared (0 is written) set by wdt reset read and cleared (0 is written) figure 19.7 timing of setting bits in reset source decision register
section 20 power supply circuit psckt00a_000020020200 rev. 3.00 sep. 10, 2007 page 393 of 528 rej09b0216-0300 section 20 power supply circuit this lsi incorporates an internal power supply step-down circuit. use of this circuit enables the internal power supply to be fixed at a constant level of approximately 3.0 v, independently of the voltage of the power supply connected to the external v cc pin. as a result, the current consumed when an external power supply is used at 3.0 v or above can be held down to virtually the same low level as when used at approximately 3.0 v. 20.1 power supply connection of 5.0-v- specification microcontrollers connect the external power supply to the v cc pin, and connect a capacitor of approximately 0.1 f between v cl and v ss , as shown in figure 20.1. the internal step-down circuit is made effective simply by adding this external circ uit. in the external circuit interface, the external power supply voltage connected to v cc and the gnd potential connected to v ss are the reference levels. for example, for port input/output levels, the v cc level is the reference for the high level, and the v ss level is that for the low level. the a/d converter analog power supply is not affected by the internal step-down circuit. v cl v ss internal logic step-down circuit internal power supply stabilization capacitor (approx. 0.1 f) v cc v cc = 4.5 to 5.5 v figure 20.1 power supply connection of 5.0-v-specification microcontrollers
section 20 power supply circuit rev. 3.00 sep. 10, 2007 page 394 of 528 rej09b0216-0300 20.2 power supply connection of 3.3-v- specification microcontrollers connect the external power supply to the v cl and v ss pins as shown in figure 20.2. the power supply voltage must be within a range of 3.0 to 3.6 v. otherwise, correct operation is not guaranteed. v cl v ss internal logic step-down circuit internal power supply v cc v cc = 3.0 to 3.6 v figure 20.2 power supply connection of 3.3-v-specification microcontrollers
section 21 list of registers rev. 3.00 sep. 10, 2007 page 395 of 528 rej09b0216-0300 section 21 list of registers the register list gives information on the on-chip i/o register addresses, how the register bits are configured, and the register states in each ope rating mode. the information is given as shown below. 1. register addresses (address order) ? the register addresses listed in the table are the address values (16 bits) in the 64-kbyte address space. the value of the sixteen higher-orde r bits of address values (24 bits) in the 16- mbyte address space is h'ff. ? registers are listed from the lower allocation addresses. ? the symbol ? in the register-name column represents a reserved address or range of reserved addresses. do not attempt to access reserved addresses. ? when the register address is 16-bit wide, the address of the upper byte is given in the list. ? registers are classified by functional modules. ? the data bus width is indicated. ? the number of access states is indicated. 2. register bits ? bit configurations of the registers are described in the same order as the register addresses. ? reserved bits are indicated by ? in the bit name column. ? when registers consist of 16 bits, bits are described from the msb side. 3. register states in each operating mode ? register states are described in the sa me order as the register addresses. ? the register states described here are for the ba sic operating modes. if there is a specific reset for an on-chip peripheral module, refer to the section on that on-chip peripheral module.
section 21 list of registers rev. 3.00 sep. 10, 2007 page 396 of 528 rej09b0216-0300 21.1 register addresse s (address order) the data-bus width column indicates the numbe r of bits. the access-state column shows the number of states of the selected basic clock that is required for access to the register. note: access to undefined or reserved addresses should not take place. correct operation of the access itself or later operations is not guaranteed when such a register is accessed. register abbre- viation bit no address module name data bus width access state ? ? ? h'f000 to h'f6ff ? ? ? timer control register_0 tcr_0 8 h'f700 timer z 8 2 timer i/o control register a_0 tiora_0 8 h'f701 timer z 8 2 timer i/o control register c_0 tiorc_0 8 h'f702 timer z 8 2 timer status register_0 tsr_0 8 h'f703 timer z 8 2 timer interrupt enable register_0 tier_0 8 h'f704 timer z 8 2 pwm mode output level control register_0 pocr_0 8 h'f705 timer z 8 2 timer counter_0 tcnt_0 16 h'f706 timer z 16 2 general register a_0 gra_0 16 h'f708 timer z 16 2 general register b_0 grb_0 16 h'f70a timer z 16 2 general register c_0 grc_0 16 h'f70c timer z 16 2 general register d_0 grd_0 16 h'f70e timer z 16 2 timer control register_1 tcr_1 8 h'f710 timer z 8 2 timer i/o control register a_1 tiora_1 8 h'f711 timer z 8 2 timer i/o control register c_1 tiorc_1 8 h'f712 timer z 8 2 timer status register_1 tsr_1 8 h'f713 timer z 8 2 timer interrupt enable register_1 tier_1 8 h'f714 timer z 8 2 pwm mode output level control register_1 pocr_1 8 h'f715 timer z 8 2 timer counter_1 tcnt_1 16 h'f716 timer z 16 2 general register a_1 gra_1 16 h'f718 timer z 16 2 general register b_1 grb_1 16 h'f71a timer z 16 2
section 21 list of registers rev. 3.00 sep. 10, 2007 page 397 of 528 rej09b0216-0300 register abbre- viation bit no address module name data bus width access state general register c_1 grc_1 16 h'f71c timer z 16 2 general register d_1 grd_1 16 h'f71e timer z 16 2 timer start register tstr 8 h'f720 timer z 8 2 timer mode register tmdr 8 h'f721 timer z 8 2 timer pwm mode register tpmr 8 h'f722 timer z 8 2 timer z, for common use tfcr 8 h'f723 timer z 8 2 timer output master enable register toer 8 h'f724 timer z 8 2 timer output control register tocr 8 h'f725 timer z 8 2 ? ? ? h'f726, h'f727 timer z ? ? second data register/free running counter data register rsecdr 8 h'f728 rtc 8 2 minute data register rmindr 8 h'f729 rtc 8 2 hour data register rhrdr 8 h'f72a rtc 8 2 day-of-week data register rwkdr 8 h'f72b rtc 8 2 rtc control register 1 rtccr1 8 h'f72c rtc 8 2 rtc control register 2 rtccr2 8 h'f72d rtc 8 2 ? ? ? h'f72e rtc ? ? clock source select register rtccsr 8 h'f72f rtc 8 2 low-voltage-detection control register lvdcr 8 h'f730 lvdc * 1 8 2 low-voltage-detection status register lvdsr 8 h'f731 lvdc * 1 8 2 reset source decision register lvdrf 8 h'f732 lvdc * 1 8 2 ? ? ? h'f733 ? ? ? clock control/status register ckcsr 8 h'f734 cpg 8 2 rc control register rccr 8 h'f735 on-chip oscillator 8 2 rc trimming data protect register rctrmdpr 8 h'f736 on-chip oscillator 8 2
section 21 list of registers rev. 3.00 sep. 10, 2007 page 398 of 528 rej09b0216-0300 register abbre- viation bit no address module name data bus width access state rc trimming data register rctrmdr 8 h'f737 on-chip oscillator 8 2 ? ? ? h'f738 to h'f73f ? ? ? serial mode register_2 smr_2 8 h'f740 sci3_2 8 3 bit rate register_2 brr_2 8 h'f741 sci3_2 8 3 serial control register 3_2 scr3_2 8 h'f742 sci3_2 8 3 transmit data register_2 tdr_2 8 h'f743 sci3_2 8 3 serial status register_2 ssr_2 8 h'f744 sci3_2 8 3 receive data register_2 rdr_2 8 h'f745 sci3_2 8 3 ? ? ? h'f746, h'f747 sci3_2 ? ? i2c bus control register 1 iccr1 8 h'f748 iic2 8 2 i2c bus control register 2 iccr2 8 h'f749 iic2 8 2 i2c bus mode register icmr 8 h'f74a iic2 8 2 i2c bus interrupt enable register icier 8 h'f74b iic2 8 2 i2c status register icsr 8 h'f74c iic2 8 2 slave address register sar 8 h'f74d iic2 8 2 i2c bus transmit data register icdrt 8 h'f74e iic2 8 2 i2c bus receive data register icdrr 8 h'f74f iic2 8 2 ? ? ? h'f750 to h'f75f ? ? ? timer mode register b1 tmb1 8 h'f760 timer b1 8 2 timer counter b1 tcb1 8 h'f761 timer b1 8 2 timer load register b1 tlb1 8 h'f761 timer b1 8 2 ? ? ? h'f762 to h'ff8f ? ? ? flash memory control register 1 flmcr1 8 h'ff90 rom 8 2 flash memory control register 2 flmcr2 8 h'ff91 rom 8 2 flash memory power control register flpwcr 8 h'ff92 rom 8 2
section 21 list of registers rev. 3.00 sep. 10, 2007 page 399 of 528 rej09b0216-0300 register abbre- viation bit no address module name data bus width access state erase block register 1 ebr1 8 h'ff93 rom 8 2 ? ? ? h'ff94 to h'ff9a rom ? ? flash memory enable register fenr 8 h'ff9b rom 8 2 ? ? ? h'ff9c to h'ff9f rom ? ? timer control register v0 tcrv0 8 h'ffa0 timer v 8 3 timer control/status register v tcsrv 8 h'ffa1 timer v 8 3 time constant register a tcora 8 h'ffa2 timer v 8 3 time constant register b tcorb 8 h'ffa3 timer v 8 3 timer counter v tcntv 8 h'ffa4 timer v 8 3 timer control register v1 tcrv1 8 h'ffa5 timer v 8 3 ? ? ? h'ffa6, h'ffa7 ? ? ? serial mode register smr 8 h'ffa8 sci3 8 3 bit rate register brr 8 h'ffa9 sci3 8 3 serial control register 3 scr3 8 h'ffaa sci3 8 3 transmit data register tdr 8 h'ffab sci3 8 3 serial status register ssr 8 h'ffac sci3 8 3 receive data register rdr 8 h'ffad sci3 8 3 ? ? ? h'ffae, h'ffaf sci3 ? ? a/d data register addra 16 h'ffb0 a/d converter 8 3 a/d data register addrb 16 h'ffb2 a/d converter 8 3 a/d data register addrc 16 h'ffb4 a/d converter 8 3 a/d data register addrd 16 h'ffb6 a/d converter 8 3 a/d control/status register adcsr 8 h'ffb8 a/d converter 8 3
section 21 list of registers rev. 3.00 sep. 10, 2007 page 400 of 528 rej09b0216-0300 register abbre- viation bit no address module name data bus width access state a/d control register adcr 8 h'ffb9 a/d converter 8 3 ? ? ? h'ffba, h'ffbb ? ? ? pwm data register l pwdrl 8 h'ffbc 14-bit pwm 8 2 pwm data register u pwdru 8 h'ffbd 14-bit pwm 8 2 pwm control register pwcr 8 h'ffbe 14-bit pwm 8 2 ? ? ? h'ffbf 14-bit pwm ? ? timer control/status register wd tcsrwd 8 h'ffc0 wdt * 1 8 2 timer counter wd tcwd 8 h'ffc1 wdt * 1 8 2 timer mode register wd tmwd 8 h'ffc2 wdt * 1 8 2 ? ? ? h'ffc3 wdt * 1 ? ? ? ? ? h'ffc4 to h'ffc7 ? ? ? address break control register abrkcr 8 h'ffc8 address break 8 2 address break status register abrksr 8 h'ffc9 address break 8 2 break address register h barh 8 h'ffca address break 8 2 break address register l barl 8 h'ffcb address break 8 2 break data register h bdrh 8 h'ffcc address break 8 2 break data register l bdrl 8 h'ffcd address break 8 2 ? ? ? h'ffce ? ? ? break address register e * 2 bare 8 h'ffcf address break 8 2 port pull-up control register 1 pucr1 8 h'ffd0 i/o port 8 2 port pull-up control register 5 pucr5 8 h'ffd1 i/o port 8 2 ? ? ? h'ffd2, h'ffd3 i/o port ? ? port data register 1 pdr1 8 h'ffd4 i/o port 8 2 port data register 2 pdr2 8 h'ffd5 i/o port 8 2 port data register 3 pdr3 8 h'ffd6 i/o port 8 2 ? ? ? h'ffd7 i/o port ? ? port data register 5 pdr5 8 h'ffd8 i/o port 8 2
section 21 list of registers rev. 3.00 sep. 10, 2007 page 401 of 528 rej09b0216-0300 register abbre- viation bit no address module name data bus width access state port data register 6 pdr6 8 h'ffd9 i/o port 8 2 port data register 7 pdr7 8 h'ffda i/o port 8 2 port data register 8 pdr8 8 h'ffdb i/o port 8 2 ? ? ? h'ffdc i/o port ? ? port data register b pdrb 8 h'ffdd i/o port 8 2 port data register c pdrc 8 h'ffde i/o port 8 2 ? ? ? h'ffdf i/o port ? ? port mode register 1 pmr1 8 h'ffe0 i/o port 8 2 port mode register 5 pmr5 8 h'ffe1 i/o port 8 2 port mode register 3 pmr3 8 h'ffe2 i/o port 8 2 ? ? ? h'ffd3 i/o port ? ? port control register 1 pcr1 8 h'ffe4 i/o port 8 2 port control register 2 pcr2 8 h'ffe5 i/o port 8 2 port control register 3 pcr3 8 h'ffe6 i/o port 8 2 ? ? ? h'ffe7 i/o port ? ? port control register 5 pcr5 8 h'ffe8 i/o port 8 2 port control register 6 pcr6 8 h'ffe9 i/o port 8 2 port control register 7 pcr7 8 h'ffea i/o port 8 2 port control register 8 pcr8 8 h'ffeb i/o port 8 2 ? ? ? h'ffec, h'ffed i/o port ? ? port control register c pcrc 8 h'ffee i/o port 8 2 ? ? ? h'ffef i/o port ? ? system control register 1 syscr1 8 h'fff0 low power 8 2 system control register 2 syscr2 8 h'fff1 low power 8 2 interrupt edge select register 1 iegr1 8 h'fff2 interrupt 8 2 interrupt edge select register 2 iegr2 8 h'fff3 interrupt 8 2 interrupt enable register 1 ienr1 8 h'fff4 interrupt 8 2 interrupt enable register 2 ienr2 8 h'fff5 interrupt 8 2 interrupt flag register 1 irr1 8 h'fff6 interrupt 8 2
section 21 list of registers rev. 3.00 sep. 10, 2007 page 402 of 528 rej09b0216-0300 register abbre- viation bit no address module name data bus width access state interrupt flag register 2 irr2 8 h'fff7 interrupt 8 2 wakeup interrupt flag register iwpr 8 h'fff8 interrupt 8 2 module standby control register 1 mstcr1 8 h'fff9 low power 8 2 module standby control register 2 mstcr2 8 h'fffa low power 8 2 ? ? ? h'ffeb low power ? ? ? ? ? h'fffc to h'ffff ? ? ? notes: 1. wdt: watchdog timer 2. only provided for microcontrollers that supports advanced mode.
section 21 list of registers rev. 3.00 sep. 10, 2007 page 403 of 528 rej09b0216-0300 21.2 register bits the addresses and bit names of the registers in the on-chip peripheral modules are listed below. the 16-bit register is indicated in two rows, 8 bits for each row. register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name ? ? ? ? ? ? ? ? ? ? tcr_0 cclr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 timer z tiora_0 ? iob2 iob1 iob0 ? ioa2 ioa1 ioa0 tiorc_0 ? iod2 iod1 iod0 ? ioc2 ioc1 ioc0 tsr_0 ? ? ? ovf imfd imfc imfb imfa tier_0 ? ? ? ovie imied imiec imieb imiea pocr_0 ? ? ? ? ? pold polc polb tcnt_0 tcnt0h7 tcnt0h6 tcnt0h5 tcnt0h4 tcnt0h3 tcnt0h2 tcnt0h1 tcnt0h0 tcnt0l7 tcnt0l6 tcnt0l5 tcnt0l4 tcnt0l3 tcnt0l2 tcnt0l1 tcnt0l0 gra_0 gra0h7 gra0h6 gra0h5 gra0h4 gra0h3 gra0h2 gra0h1 gra0h0 gra0l7 gra0l6 gra0l5 gra0l4 gra0l3 gra0l2 gra0l1 gra0l0 grb_0 grb0h7 grb0h6 grb0h5 grb0h4 grb0h3 grb0h2 grb0h1 grb0h0 grb0l7 grb0l6 grb0l5 grb0l4 grb0l3 grb0l2 grb0l1 grb0l0 grc_0 grc0h7 grc0h6 grc0h5 grc0h4 grc0h3 grc0h2 grc0h1 grc0h0 grc0l7 grc0l6 grc0l5 grc0l4 grc0l3 grc0l2 grc0l1 grc0l0 grd_0 grd0h7 grd0h6 grd0h5 grd0h4 grd0h3 grd0h2 grd0h1 grd0h0 grd0l7 grd0l6 grd0l5 grd0l4 grd0l3 grd0l2 grd0l1 grd0l0 tcr_1 cclr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tiora_1 ? iob2 iob1 iob0 ? ioa2 ioa1 ioa0 tiorc_1 ? iod2 iod1 iod0 ? ioc2 ioc1 ioc0 tsr_1 ? ? udf ovf imfd imfc imfb imfa tier_1 ? ? ? ovie imied imiec imieb imiea pocr_1 ? ? ? ? ? pold polc polb tcnt_1 tcnt1h7 tcnt1h6 tcnt1h5 tcnt1h4 tcnt1h3 tcnt1h2 tcnt1h1 tcnt1h0 tcnt1l7 tcnt1l6 tcnt1l5 tcnt1l4 tcnt1l3 tcnt1l2 tcnt1l1 tcnt1l0 gra_1 gra1h7 gra1h6 gra1h5 gra1h4 gra1h3 gra1h2 gra1h1 gra1h0 gra1l7 gra1l6 gra1l5 gra1l4 gra1l3 gra1l2 gra1l1 gra1l0
section 21 list of registers rev. 3.00 sep. 10, 2007 page 404 of 528 rej09b0216-0300 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name grb_1 grb1h7 grb1h6 grb1h5 grb1h4 gr b1h3 grb1h2 grb1h1 grb1h0 timer z grb1l7 grb1l6 grb1l5 grb1l4 grb1l3 grb1l2 grb1l1 grb1l0 grc_1 grc1h7 grc1h6 grc1h5 grc1h4 grc1h3 grc1h2 grc1h1 grc1h0 grc1l7 grc1l6 grc1l5 grc1l4 grc1l3 grc1l2 grc1l1 grc1l0 grd_1 grd1h7 grd1h6 grd1h5 grd1h4 grd1h3 grd1h2 grd1h1 grd1h0 grd1l7 grd1l6 grd1l5 grd1l4 grd1l3 grd1l2 grd1l1 grd1l0 tstr ? ? ? ? ? ? str1 str0 tmdr bfd1 bfc1 bfd0 bfc0 ? ? ? sync tpmr ? pwmd1 pwmc1 pwmb1 ? pwmd0 pwmc0 pwmb0 tfcr ? stclk adeg adtrg ols1 ols0 cmd1 cmd0 toer ed1 ec1 eb1 ea1 ed0 ec0 eb0 ea0 tocr tod1 toc1 tob1 toa1 tod0 toc0 tob0 toa0 rsecdr bsy sc12 sc11 sc10 sc03 sc02 sc01 sc00 rtc rmindr bsy mn12 mn11 mn10 mn03 mn02 mn01 mn00 rhrdr bsy ? hr11 hr10 hr03 hr02 hr01 hr00 rwkdr bsy ? ? ? ? wk2 wk1 wk0 rtccr1 run 12/24 pm rst int ? ? ? rtccr2 ? ? foie wkie dyie hrie mnie seie rtccsr ? rcs6 rcs5 ? rcs3 rcs2 rcs1 rcs0 lvdcr ? ? vddii ? lvdsel * 1 ? lvdde lvdue lvdc lvdsr ? ? ? ? ? ? lvddf lvduf lvdrf ? ? ? ? ? ? prst wrst ? ? ? ? ? ? ? ? ? ? ckcsr pmrc1 pmrc0 oscbake oscsel ckswie ckswif oschlt cksta cpg rccr rcstp fsel vclsel ? ? ? rcpsc1 rcpsc0 rctrmdpr wri prwe lockdw trmdrwe ? ? ? ? on-chip oscillator rctrmdr trmd7 trmd6 trmd5 trmd4 trmd3 trmd2 trmd1 trmd0 ? ? ? ? ? ? ? ? ? ? smr_2 com chr pe pm stop mp cks1 cks0 sci3_2 brr_2 brr7 brr6 brr5 brr4 brr3 brr2 brr1 brr0 scr3_2 tie rie te re mpie teie cke1 cke0
section 21 list of registers rev. 3.00 sep. 10, 2007 page 405 of 528 rej09b0216-0300 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name tdr_2 tdr7 tdr6 tdr5 tdr4 tdr3 tdr2 tdr1 tdr0 sci3_2 ssr_2 tdre rdrf oer fer per tend mpbr mpbt rdr_2 rdr7 rdr6 rdr5 rdr4 rdr3 rdr2 rdr1 rdr0 iccr1 ice rcvd mst trs cks3 cks2 cks1 cks0 iic2 iccr2 bbsy scp sdao sdaop sclo ? iicrst ? icmr mls wait ? ? bcwp bc2 bc1 bc0 icier tie teie rie nakie stie acke ackbr ackbt icsr tdre tend rdrf nackf stop al/ove aas adz sar sva6 sva5 sva4 sva3 sva2 sva1 sva0 fs icdrt icdrt7 icdrt6 icdrt5 icdrt 4 icdrt3 icdrt2 icdrt1 icdrt0 icdrr icdrr7 icdrr6 icdrr5 icdrr4 icdrr3 icdrr2 icdrr1 icdrr0 ? ? ? ? ? ? ? ? ? ? tmb1 tmb17 ? ? ? ? tmb12 tmb11 tmb10 timer b1 tcb1 tcb17 tcb16 tcb15 tcb14 tcb13 tcb12 tcb11 tcb10 tlb1 tlb17 tlb16 tlb15 tlb14 tlb13 tlb12 tlb11 tlb10 ? ? ? ? ? ? ? ? ? ? flmcr1 ? swe esu psu ev pv e p rom flmcr2 fler ? ? ? ? ? ? ? flpwcr pdwnd ? ? ? ? ? ? ? ebr1 * 1 eb7 eb6 eb5 eb4 eb3 eb2 eb1 eb0 fenr flshe ? ? ? ? ? ? ? tcrv0 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 timer v tcsrv cmfb cmfa ovf ? os3 os2 os1 os0 tcora tcora7 tcora6 tcora5 tcora4 tcora3 tcora2 tcora1 tcora0 tcorb tcorb7 tcorb6 tcorb5 tcorb4 tcorb3 tcorb2 tcorb1 tcorb0 tcntv tcntv7 tcntv6 tcntv5 tcntv4 tcntv3 tcntv2 tcntv1 tcntv0 tcrv1 ? ? ? tveg1 tveg0 trge ? icks0 ? ? ? ? ? ? ? ? ? ? smr com chr pe pm stop mp cks1 cks0 sci3 brr brr7 brr6 brr5 brr4 brr3 brr2 brr1 brr0 scr3 tie rie te re mpie teie cke1 cke0
section 21 list of registers rev. 3.00 sep. 10, 2007 page 406 of 528 rej09b0216-0300 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name tdr tdr7 tdr6 tdr5 tdr4 tdr3 tdr2 tdr1 tdr0 sci3 ssr tdre rdrf oer fer per tend mpbr mpbt rdr rdr7 rdr6 rdr5 rdr4 rdr3 rdr2 rdr1 rdr0 addra ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 ? ? ? ? ? ? a/d converter addrb ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 ? ? ? ? ? ? addrc ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 ? ? ? ? ? ? addrd ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 ? ? ? ? ? ? adcsr adf adie adst scan cks ch2 ch1 ch0 adcr trge ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? pwdrl pwdrl7 pwdrl6 pwdrl5 pwdrl4 pwdrl3 pwdrl2 pwdrl1 pwdrl0 pwdru ? ? pwdru5 pwdru4 pwdru3 pwdru2 pwdru1 pwdru0 14-bit pwm pwcr ? ? ? ? ? ? ? pwcr0 tcsrwd b6wi tcwe b4wi tcsrwe b2wi wdon b0wi wrst wdt * 2 tcwd tcwd7 tcwd6 tcwd5 tcwd4 tcwd3 tcwd2 tcwd1 tcwd0 tmwd ? ? ? ? cks3 cks2 cks1 cks0 ? ? ? ? ? ? ? ? ? ? abrkcr rtinte csel1 csel0 acmp2 acmp1 acmp0 dcmp1 dcmp0 abrksr abif abie ? ? ? ? ? ? address break barh barh7 barh6 barh5 barh4 barh3 barh2 barh1 barh0 barl barl7 barl6 barl5 barl4 barl3 barl2 barl1 barl0 bdrh bdrh7 bdrh6 bdrh5 bdrh4 bdrh3 bdrh2 bdrh1 bdrh0 bdrl bdrl7 bdrl6 bdrl5 bdrl4 bdrl3 bdrl2 bdrl1 bdrl0 bare * 3 bdre7 bdre6 bdre5 bdre4 bdre3 bdre2 bdre1 bdre0 pucr1 pucr17 pucr16 pucr15 pucr14 ? pucr12 pucr11 pucr10 i/o port pucr5 ? ? pucr55 pucr54 pucr53 pucr52 pucr51 pucr50 pdr1 p17 p16 p15 p14 ? p12 p11 p10
section 21 list of registers rev. 3.00 sep. 10, 2007 page 407 of 528 rej09b0216-0300 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name pdr2 ? ? ? p24 p23 p22 p21 p20 i/o port pdr3 p37 p36 p35 p34 p33 p32 p31 p30 pdr5 p57 p56 p55 p54 p53 p52 p51 p50 pdr6 p67 p66 p65 p64 p63 p62 p61 p60 pdr7 ? p76 p75 p74 ? p72 p71 p70 pdr8 p87 p86 p85 ? ? ? ? ? pdrb pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 pdrc ? ? ? ? ? ? pc1 pc0 pmr1 irq3 irq2 irq1 irq0 txd2 pwm txd tmow pmr5 pof57 pof56 wkp5 wkp4 wkp3 wkp2 wkp1 wkp0 pmr3 ? ? ? pof24 pof23 ? ? ? pcr1 pcr17 pcr16 pcr15 pcr14 ? pcr12 pcr11 pcr10 pcr2 ? ? ? pcr24 pcr23 pcr22 pcr21 pcr20 pcr3 pcr37 pcr36 pcr35 pcr34 pcr33 pcr32 pcr31 pcr30 pcr5 pcr57 pcr56 pcr55 pcr54 pcr53 pcr52 pcr51 pcr50 pcr6 pcr67 pcr66 pcr65 pcr64 pcr63 pcr62 pcr61 pcr60 pcr7 ? pcr76 pcr75 pcr74 ? pcr72 pcr71 pcr70 pcr8 pcr87 pcr86 pcr85 ? ? ? ? ? pcrc ? ? ? ? ? ? pcrc1 pcrc0 syscr1 ssby sts2 sts1 sts0 nesel ? ? ? low power syscr2 smsel lson dton ma2 ma1 ma0 sa1 sa0 iegr1 nmieg ? ? ? ieg3 ieg2 ieg1 ieg0 interrupt iegr2 ? ? wpeg5 wpeg4 wpeg3 wpeg2 wpeg1 wpeg0 ienr1 iendt ienta ienwp ? ien3 ien2 ien1 ien0 ienr2 ? ? ientb1 ? ? ? ? ? irr1 irrdt irrta ? ? irri3 irri2 irri1 irri0 irr2 ? ? irrtb1 ? ? ? ? ? iwpr ? ? iwpf5 iwpf4 iwpf3 iwpf2 iwpf1 iwpf0
section 21 list of registers rev. 3.00 sep. 10, 2007 page 408 of 528 rej09b0216-0300 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name mstcr1 ? mstiic msts3 mstad mstwd ? msttv mstta low power mstcr2 msts3_2 ? ? msttb1 ? ? msttz mstpwm ? ? ? ? ? ? ? ? ? ? notes: 1. the lvdsel bit is only provided for the 5.0-v specification products. 2. wdt: watchdog timer 3. the bare register is only provided for microcontrollers that support advanced mode. 4. the bit configuration of ebr1 differs according to products. for the bit configuration of each product, see the list below. ? h8/36079g, h8/36079l register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name ebr1 eb7 eb6 eb5 eb4 eb3 eb2 eb1 eb0 rom ? h8/36078g, h8/36078l, h8/36077g, h8/36077l register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name ebr1 ? eb6 eb5 eb4 eb3 eb2 eb1 eb0 rom ? h8/36074g, h8/36074l register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name ebr1 ? ? ? eb4 eb3 eb2 eb1 eb0 rom
section 21 list of registers rev. 3.00 sep. 10, 2007 page 409 of 528 rej09b0216-0300 21.3 registers states in each operating mode register name reset active sleep subactive subsleep standby module tcr_0 initialized ? ? ? ? ? timer z tiora_0 initialized ? ? ? ? ? tiorc_0 initialized ? ? ? ? ? tsr_0 initialized ? ? ? ? ? tier_0 initialized ? ? ? ? ? pocr_0 initialized ? ? ? ? ? tcnt_0 initialized ? ? ? ? ? gra_0 initialized ? ? ? ? ? grb_0 initialized ? ? ? ? ? grc_0 initialized ? ? ? ? ? grd_0 initialized ? ? ? ? ? tcr_1 initialized ? ? ? ? ? tiora_1 initialized ? ? ? ? ? tiorc_1 initialized ? ? ? ? ? tsr_1 initialized ? ? ? ? ? tier_1 initialized ? ? ? ? ? pocr_1 initialized ? ? ? ? ? tcnt_1 initialized ? ? ? ? ? gra_1 initialized ? ? ? ? ? grb_1 initialized ? ? ? ? ? grc_1 initialized ? ? ? ? ? grd_1 initialized ? ? ? ? ? tstr initialized ? ? ? ? ? tmdr initialized ? ? ? ? ? tpmr initialized ? ? ? ? ? tfcr initialized ? ? ? ? ? toer initialized ? ? ? ? ? tocr initialized ? ? ? ? ?
section 21 list of registers rev. 3.00 sep. 10, 2007 page 410 of 528 rej09b0216-0300 register name reset active sleep subactive subsleep standby module rsecdr ? ? ? ? ? ? rtc rmindr ? ? ? ? ? ? rhrdr ? ? ? ? ? ? rwkdr ? ? ? ? ? ? rtccr1 ? ? ? ? ? ? rtccr2 ? ? ? ? ? ? rtccsr initialized ? ? ? ? ? lvdcr initialized ? ? ? ? ? lvdc * 1 lvdsr initialized ? ? ? ? ? lvdrf ? ? ? ? ? ? ckcsr initialized ? ? ? ? ? cpg rccr initialized ? ? ? ? ? rctrmdpr initialized ? ? ? ? ? on-chip oscillator rctrmdr initialized ? ? ? ? ? smr_2 initialized ? ? initialized initialized initialized sci3_2 brr_2 initialized ? ? initialized initialized initialized scr3_2 initialized ? ? initialized initialized initialized tdr_2 initialized ? ? initialized initialized initialized ssr_2 initialized ? ? initialized initialized initialized rdr_2 initialized ? ? initialized initialized initialized iccr1 initialized ? ? ? ? ? iic2 iccr2 initialized ? ? ? ? ? icmr initialized ? ? ? ? ? icier initialized ? ? ? ? ? icsr initialized ? ? ? ? ? sar initialized ? ? ? ? ? icdrt initialized ? ? ? ? ? icdrr initialized ? ? ? ? ? tmb1 initialized ? ? ? ? ? timer b1 tcb1 initialized ? ? ? ? ? tlb1 initialized ? ? ? ? ?
section 21 list of registers rev. 3.00 sep. 10, 2007 page 411 of 528 rej09b0216-0300 register name reset active sleep subactive subsleep standby module flmcr1 initialized ? ? initialized initialized initialized rom flmcr2 initialized ? ? ? ? ? flpwcr initialized ? ? ? ? ? ebr1 initialized ? ? initialized initialized initialized fenr initialized ? ? ? ? ? tcrv0 initialized ? ? initialized initialized initialized timer v tcsrv initialized ? ? initialized initialized initialized tcora initialized ? ? initialized initialized initialized tcorb initialized ? ? initialized initialized initialized tcntv initialized ? ? initialized initialized initialized tcrv1 initialized ? ? initialized initialized initialized smr initialized ? ? initialized initialized initialized sci3 brr initialized ? ? initialized initialized initialized scr3 initialized ? ? initialized initialized initialized tdr initialized ? ? initialized initialized initialized ssr initialized ? ? initialized initialized initialized rdr initialized ? ? initialized initialized initialized addra initialized ? ? initialized initialized initialized a/d converter addrb initialized ? ? initialized initialized initialized addrc initialized ? ? initialized initialized initialized addrd initialized ? ? initialized initialized initialized adcsr initialized ? ? initialized initialized initialized adcr initialized ? ? initialized initialized initialized pwdrl initialized ? ? ? ? ? 14bit pwm pwdru initialized ? ? ? ? ? pwcr initialized ? ? ? ? ? tcsrwd initialized ? ? ? ? ? wdt * 1 tcwd initialized ? ? ? ? ? tmwd initialized ? ? ? ? ? abrkcr initialized ? ? ? ? ? address break abrksr initialized ? ? ? ? ?
section 21 list of registers rev. 3.00 sep. 10, 2007 page 412 of 528 rej09b0216-0300 register name reset active sleep subactive subsleep standby module barh initialized ? ? ? ? ? address break barl initialized ? ? ? ? ? bdrh initialized ? ? ? ? ? bdrl initialized ? ? ? ? ? bare * 2 initialized ? ? ? ? ? pucr1 initialized ? ? ? ? ? i/o port pucr5 initialized ? ? ? ? ? pdr1 initialized ? ? ? ? ? pdr2 initialized ? ? ? ? ? pdr3 initialized ? ? ? ? ? pdr5 initialized ? ? ? ? ? pdr6 initialized ? ? ? ? ? pdr7 initialized ? ? ? ? ? pdr8 initialized ? ? ? ? ? pdrb initialized ? ? ? ? ? pdrc initialized ? ? ? ? ? pmr1 initialized ? ? ? ? ? pmr5 initialized ? ? ? ? ? pmr3 initialized ? ? ? ? ? pcr1 initialized ? ? ? ? ? pcr2 initialized ? ? ? ? ? pcr3 initialized ? ? ? ? ? pcr5 initialized ? ? ? ? ? pcr6 initialized ? ? ? ? ? pcr7 initialized ? ? ? ? ? pcr8 initialized ? ? ? ? ? pcrc initialized ? ? ? ? ? syscr1 initialized ? ? ? ? ? low power syscr2 initialized ? ? ? ? ?
section 21 list of registers rev. 3.00 sep. 10, 2007 page 413 of 528 rej09b0216-0300 register name reset active sleep subactive subsleep standby module iegr1 initialized ? ? ? ? ? interrupt iegr2 initialized ? ? ? ? ? ienr1 initialized ? ? ? ? ? ienr2 initialized ? ? ? ? ? irr1 initialized ? ? ? ? ? irr2 initialized ? ? ? ? ? iwpr initialized ? ? ? ? ? mstcr1 initialized ? ? ? ? ? low power mstcr2 initialized ? ? ? ? ? notes: ? is not initialized 1. wdt: watchdog timer 2. the bare register is only provided for microcontrollers that support advanced mode.
section 21 list of registers rev. 3.00 sep. 10, 2007 page 414 of 528 rej09b0216-0300
section 22 electrical characteristics rev. 3.00 sep. 10, 2007 page 415 of 528 rej09b0216-0300 section 22 electrical characteristics 22.1 absolute maximum ratings table 22.1 absolute maximum ratings item symbol value unit note power supply voltage v cc ?0.3 to +7.0 v * analog power supply voltage av cc ?0.3 to +7.0 v input voltage ports other than ports b and x1 v in ?0.3 to v cc +0.3 v port b ?0.3 to av cc +0.3 v x1 ?0.3 to 4.3 v regular specifications: ?20 to +75 c operating temperature t opr wide-range specifications: ?40 to +85 c storage temperature t stg ?55 to +125 c notes: * permanent damage may result if maximum ratings are exceeded. normal operation should be under the conditions specified in electrical characteristics. exceeding these values can result in incorrect operation and reduced reliability.
section 22 electrical characteristics rev. 3.00 sep. 10, 2007 page 416 of 528 rej09b0216-0300 22.2 electrical characteristics (f-ztat? 5.0-v version) 22.2.1 power supply voltage and operating ranges (1) power supply voltage and oscillation frequency range 4.0 20.0 4.5 5.5 v cc (v) osc (mhz) 32.768 4.5 5.5 v cc (v) w (khz) av cc = 4.5 to 5.5 v active mode sleep mode av cc = 4.5 to 5.5 v all operating modes
section 22 electrical characteristics rev. 3.00 sep. 10, 2007 page 417 of 528 rej09b0216-0300 (2) power supply voltage and operating frequency range 4.0 20.0 4.5 5.5 v cc (v) (mhz) 16.384 4.5 5.5 v cc (v) sub (khz) 8.192 4.096 78.125 2500 4.5 5.5 v cc (v) (khz) av cc = 4.5 to 5.5 v active mode sleep mode (when ma2 in syscr2 = 0 ) av cc = 4.5 to 5.5 v subactive mode subsleep mode av cc = 4.5 to 5.5 v active mode sleep mode (when ma2 in syscr2 = 1 )
section 22 electrical characteristics rev. 3.00 sep. 10, 2007 page 418 of 528 rej09b0216-0300 (3) analog power supply voltage and a/d converter accuracy guaranteed range 4.0 20.0 4.5 5.5 av cc (v) (mhz) v cc = 4.5 to 5.5 v active mode sleep mode (4) range of power supply voltage and oscillation frequency when low-voltage detection circuit is used operation guaranteed range operation guaranteed range except a/d conversion accuracy 20.0 16.0 4.0 3.0 4.5 5.5 vcc (v) osc (mhz)
section 22 electrical characteristics rev. 3.00 sep. 10, 2007 page 419 of 528 rej09b0216-0300 22.2.2 dc characteristics table 22.2 dc characteristics (1) v cc = 4.5 to 5.5 v, v ss = 0.0 v, t a = ?20 to +75c/?40 to +85c, unless otherwise indicated. values item symbol applicable pins test condition min. typ. max. unit notes input high voltage v ih res , nmi , wkp0 to wkp5 , irq0 to irq3 , adtrg , tmib1, tmriv, v cc 0.8 ? v cc + 0.3 v tmciv, ftioa0 to ftiod0, ftioa1 to ftiod1, sck3, sck3_2, trgv rxd, rxd_2, scl, sda, p10 to p12, p14 to p17, p20 to p24, p30 to p37, v cc 0.7 ? v cc + 0.3 v p50 to p57, p60 to p67, p70 to p72 p74 to p76, p85 to p87, pc0, pc1 pb0 to pb7 av cc = 4.5 to 5.5 v av cc 0.7 ? av cc + 0.3 v osc1 v cc ? 0.5 ? v cc + 0.3 v input low voltage v il res , nmi , wkp0 to wkp5 , irq0 to irq3 , adtrg , tmib1, tmriv, ?0.3 ? v cc 0.2 v tmciv, ftioa0 to ftiod0, ftioa1 to ftiod1, sck3, sck3_2, trgv note: connect the test pin to vss.
section 22 electrical characteristics rev. 3.00 sep. 10, 2007 page 420 of 528 rej09b0216-0300 values item symbol applicable pins test condition min. typ. max. unit notes input low voltage v il rxd, rxd_2, scl, sda, p10 to p12, p14 to p17, p20 to p24, p30 to p37, ?0.3 ? v cc 0.3 v p50 to p57, p60 to p67, p70 to p72, p74 to p76, p85 to p87, pc0, pc1 pb0 to pb7 av cc = 4.5 to 5.5 v ?0.3 ? av cc 0.3 v osc1 ?0.3 ? 0.5 v output high voltage v oh p10 to p12, p14 to p17, p20 to p24, p30 to p37, ?i oh = 1.5 ma v cc ? 1.0 ? ? v p50 to p55, p60 to p67, p70 to p72, p74 to p76, p85 to p87, pc0, pc1 ?i oh = 0.1 ma v cc ? 0.5 ? ? p56, p57 ?i oh = 0.1 ma v cc ? 2.5 ? ? v output low voltage v ol p10 to p12, p14 to p17, p20 to p24, p30 to p37, i ol = 1.6 ma ? ? 0.6 v p50 to p57, p70 to p72, p74 to p76, p85 to p87 pc0, pc1 i ol = 0.4 ma ? ? 0.4 p60 to p67 i ol = 20.0 ma ? ? 1.5 v i ol = 10.0 ma ? ? 1.0 i ol = 1.6 ma ? ? 0.4 i ol = 0.4 ma ? ? 0.4 scl, sda i ol = 6.0 ma ? ? 0.6 i ol = 3.0 ma ? ? 0.4
section 22 electrical characteristics rev. 3.00 sep. 10, 2007 page 421 of 528 rej09b0216-0300 values item symbol applicable pins test condition min typ max unit notes input/ output leakage current | i il | osc1, tmib1, res , nmi , wkp0 to wkp5 , irq0 to irq3 , adtrg , trgv, tmriv, tmciv, ftioa0 to ftiod0, ftioa1 to ftiod1 rxd, sck3, rxd_2, sck3_2, scl, sda v in = 0.5 v to (v cc ? 0.5 v) ? ? 1.0 a p10 to p12, p14 to p17, p20 to p24, p30 to p37, p50 to p57, p60 to p67, p70 to p72, p74 to p76, p85 to p87, pc0, pc1 v in = 0.5 v to (v cc ? 0.5 v) ? ? 1.0 a pb0 to pb7 v in = 0.5 v to (av cc ? 0.5 v) ? ? 1.0 a pull-up mos current ?i p p10 to p12, p14 to p17, p50 to p55 v cc = 5.0 v, v in = 0.0 v 50.0 ? 300.0 a input capaci- tance c in all input pins except power supply pins f = 4 mhz, v in = 0.0 v, t a = 25c ? ? 15.0 pf i ope1 v cc active mode 1 v cc = 5.0 v, f osc = 20 mhz ? 19.0 28.0 ma * active mode supply current active mode 1 v cc = 5.0 v, f osc = 10 mhz ? 11.0 ? * reference value i ope2 v cc active mode 2 v cc = 5.0 v, f osc = 20 mhz ? 3.0 5.5 ma * active mode 2 v cc = 5.0 v, f osc = 10 mhz ? 2.5 ? * reference value
section 22 electrical characteristics rev. 3.00 sep. 10, 2007 page 422 of 528 rej09b0216-0300 values item symbol applicable pins test condition min. typ. max. unit notes i sleep1 v cc sleep mode 1 v cc = 5.0 v, f osc = 20 mhz ? 12.0 20.0 ma * sleep mode supply current sleep mode 1 v cc = 5.0 v, f osc = 10 mhz ? 6.5 ? * reference value i sleep2 v cc sleep mode 2 v cc = 5.0 v, f osc = 20 mhz ? 2.5 4.0 ma * sleep mode 2 v cc = 5.0 v, f osc = 10 mhz ? 2.2 ? * reference value i sub v cc v cc = 5.0 v 32-khz crystal resonator ( sub = w /2) ? 95.0 145.0 a * subactive mode supply current v cc = 5.0 v 32-khz crystal resonator ( sub = w /8) ? 85.0 ? * reference value subsleep mode supply current i subsp v cc v cc = 5.0 v 32-khz crystal resonator ( sub = w /2) ? 85.0 140.0 a * standby mode supply current i stby v cc 32-khz crystal resonator not used ? ? 135.0 a * ram data retention voltage v ram v cc 2.0 ? ? v
section 22 electrical characteristics rev. 3.00 sep. 10, 2007 page 423 of 528 rej09b0216-0300 note: * pin states during supply current measurement are given below (excluding current in the pull-up mos transistors and output buffers). mode res pin internal state other pins oscillator pins active mode 1 v cc operates v cc main clock: ceramic or crystal resonator, and on-chip oscillator active mode 2 operates ( osc /64) subclock: pin x1 = v ss sleep mode 1 v cc only timers operate v cc sleep mode 2 only timers operate ( osc /64) subactive mode v cc operates v cc main clock: ceramic or crystal resonator, and on-chip oscillator subsleep mode v cc only timers operate v cc subclock: crystal resonator standby mode v cc cpu and timers both stop v cc main clock: ceramic or crystal resonator, and on-chip oscillator subclock: pin x1 = v ss
section 22 electrical characteristics rev. 3.00 sep. 10, 2007 page 424 of 528 rej09b0216-0300 table 22.2 dc characteristics (2) v cc = 4.5 to 5.5 v, v ss = 0.0 v, t a = ?20 to +75c/?40 to +85c, unless otherwise indicated. values item symbol applicable pins test condition min. typ. max. unit permissible output low current (per pin) i ol output pins except port 6, scl, and sda ? ? 2.0 ma port 6 ? ? 20.0 permissible output low current (total) i ol output pins except port 6, scl, and sda ? ? 40.0 ma port 6, scl, and sda ? ? 80.0 permissible output high current (per pin) ? ?i oh ? all output pins ? ? 5.0 ma permissible output high current (total) ? ? i oh ? all output pins ? ? 50.0 ma
section 22 electrical characteristics rev. 3.00 sep. 10, 2007 page 425 of 528 rej09b0216-0300 22.2.3 ac characteristics table 22.3 ac characteristics v cc = 4.5 to 5.5 v, v ss = 0.0 v, t a = -20 to +75c/-40 to +85c, unless otherwise indicated. values item symbol applicable pins test condition min. typ. max. unit reference figure system clock oscillation frequency f osc osc1, osc2 4.0 ? 20.0 mhz * 1 t cyc 1 ? 64 t osc * 2 system clock ( ) cycle time ? ? 12.8 s subclock oscillation frequency f w x1, x2 ? 32.768 ? khz watch clock ( w ) cycle time t w x1, x2 ? 30.5 ? s subclock ( sub ) cycle time t subcyc 2 ? 8 t w * 2 instruction cycle time 2 ? ? t cyc t subcyc oscillation stabilization time (crystal resonator) t rc osc1, osc2 ? ? 10.0 ms oscillation stabilization time (ceramic resonator) t rc osc1, osc2 ? ? 5.0 ms oscillation stabilization time (on-chip oscillator) t rc ? ? 500 s oscillation stabilization time t rcx x1, x2 ? ? 2.0 s external clock high width t cph osc1 20.0 ? ? ns figure 22.1 external clock low width t cpl osc1 20.0 ? ? ns t cpr osc1 ? ? 10.0 ns external clock rise time ? ? 15.0 t cpf osc1 ? ? 10.0 ns external clock fall time ? ? 15.0
section 22 electrical characteristics rev. 3.00 sep. 10, 2007 page 426 of 528 rej09b0216-0300 values item symbol applicable pins test condition min. typ. max. unit reference figure res pin low width t rel res at power-on and in modes other than those below t rc ? ? ms figure 22.2 in active mode and sleep mode 2500 ? ? ns input pin high width t ih nmi , tmib1, irq0 to irq3 , wkp0 to wkp5 , tmciv, tmriv, trgv, adtrg , ftioa0 to ftiod0, ftioa1 to ftiod1 2 ? ? t cyc t subcyc figure 22.3 input pin low width t il nmi , tmib1, irq0 to irq3 , wkp0 to wkp5 , tmciv, tmriv, trgv, adtrg , ftioa0 to ftiod0, ftioa1 to ftiod1 2 ? ? t cyc t subcyc
section 22 electrical characteristics rev. 3.00 sep. 10, 2007 page 427 of 528 rej09b0216-0300 values item symbol applicable pins test condition min. typ. max. unit reference figure on-chip oscillator oscillation frequency f rc vcc = 5.0 v, ta = 25 c, fsel = 1, vclsel = 0 19.70 20.0 20.30 mhz fsel = 1, ta = -20 to +75 c, vclsel = 0 19.40 20.0 20.60 fsel = 1, ta = -40 to +85c, vclsel = 0 19.20 20.00 20.80 vcc = 5.0 v, ta = 25 c, fsel = 0, vclsel = 0 15.76 16.0 16.24 fsel = 0, ta = -20 to +75c, vclsel = 0 15.52 16.0 16.48 fsel = 0, ta = -40 to +85c, vclsel = 0 15.36 16.0 16.64 notes: 1. when an external clock is input, the minimum frequency of the external clock oscillator is 4.0 mhz. 2. determined by ma2 to ma0, sa1, and sa0 in system control register 2 (syscr2).
section 22 electrical characteristics rev. 3.00 sep. 10, 2007 page 428 of 528 rej09b0216-0300 table 22.4 i 2 c bus interface timing v cc = 4.5 to 5.5 v, v ss = 0.0 v, t a = -20 to +75c/-40 to +85c, unless otherwise indicated. values item symbol test condition min. typ. max. unit reference figure scl input cycle time t scl 12t cyc + 600 ? ? ns figure 22.4 scl input high width t sclh 3t cyc + 300 ? ? ns scl input low width t scll 5t cyc + 300 ? ? ns scl and sda input fall time t sf ? ? 300 ns scl and sda input spike pulse removal time t sp ? ? 1t cyc ns sda input bus-free time t buf 5t cyc ? ? ns start condition input hold time t stah 3t cyc ? ? ns repeated start condition input setup time t stas 3t cyc ? ? ns setup time for stop condition input t stos 3t cyc ? ? ns data-input setup time t sdas 1t cyc +20 ? ? ns data-input hold time t sdah 0 ? ? ns capacitive load of scl and sda c b 0 ? 400 pf scl and sda output fall time t sf ? ? 250 ns
section 22 electrical characteristics rev. 3.00 sep. 10, 2007 page 429 of 528 rej09b0216-0300 table 22.5 serial communication interface (sci) timing v cc = 4.5 to 5.5 v, v ss = 0.0 v, t a = -20 to +75c/-40 to +85c, unless otherwise indicated. values item symbol applicable pins test condition min. typ. max. unit reference figure asynchro- nous t scyc sck3 4 ? ? t cyc figure 22.5 input clock cycle clock synchro- nous 6 ? ? input clock pulse width t sckw sck3 0.4 ? 0.6 t scyc transmit data delay time (clock synchronous) t txd txd ? ? 1 t cyc figure 22.6 receive data setup time (clock synchronous) t rxs rxd 50.0 ? ? ns receive data hold time (clock synchronous) t rxh rxd 50.0 ? ? ns
section 22 electrical characteristics rev. 3.00 sep. 10, 2007 page 430 of 528 rej09b0216-0300 22.2.4 a/d converter characteristics table 22.6 a/d converter characteristics v cc = 4.5 to 5.5 v, v ss = 0.0 v, t a = -20 to +75c/-40 to +85c, unless otherwise indicated. values item symbol applicable pins test condition min. typ. max. unit reference figure analog power supply voltage av cc av cc 4.5 v cc 5.5 v * 1 analog input voltage av in an0 to an7 v ss ? 0.3 ? av cc + 0.3 v analog power supply current ai ope av cc av cc = 5.0 v f osc = 20 mhz ? ? 2.0 ma ai stop1 av cc ? 50 ? a * 2 reference value ai stop2 av cc ? ? 5.0 a * 3 analog input capacitance c ain an0 to an7 ? ? 30.0 pf permissible signal source impedance r ain an0 to an7 ? ? 5.0 k ? resolution (data length) 10 10 10 bit conversion time (single mode) av cc = 4.5 to 5.5 v 70 ? ? t cyc nonlinearity error ? ? 7.5 lsb offset error ? ? 7.5 lsb full-scale error ? ? 7.5 lsb quantization error ? ? 0.5 lsb absolute accuracy ? ? 8.0 lsb
section 22 electrical characteristics rev. 3.00 sep. 10, 2007 page 431 of 528 rej09b0216-0300 values item symbol applicable pins test condition min. typ. max. unit reference figure conversion time (single mode) av cc = 4.5 to 5.5 v 134 ? ? t cyc nonlinearity error ? ? 3.5 lsb offset error ? ? 3.5 lsb full-scale error ? ? 3.5 lsb quantization error ? ? 0.5 lsb absolute accuracy ? ? 4.0 lsb notes: 1. set av cc = v cc when the a/d converter is not used. 2. ai stop1 is the current in active and sleep modes while the a/d converter is idle. 3. ai stop2 is the current at reset and in standby, subactive, and subsleep modes while the a/d converter is idle. 22.2.5 watchdog timer characteristics table 22.7 watchdog timer characteristics v cc = 4.5 to 5.5 v, v ss = 0.0 v, t a = -20 to +75c/-40 to +85c, unless otherwise indicated. values item symbol applicable pins test condition min. typ. max. unit reference figure on-chip oscillator overflow time t ovf 0.2 0.4 ? s * note: * time until an internal reset is generated after the counter counts from 0 to 255 when the on-chip oscillator is selected
section 22 electrical characteristics rev. 3.00 sep. 10, 2007 page 432 of 528 rej09b0216-0300 22.2.6 flash memory characteristics table 22.8 flash memory characteristics v cc = 4.5 to 5.5 v, v ss = 0.0 v, t a = -20 to +75c/-40 to +85c, unless otherwise indicated. values item symbol test condition min. typ. max. unit programming time (per 128 bytes) * 1 * 2 * 4 t p ? 7.0 200.0 ms erase time (per block) * 1 * 3 * 6 t e ? 10.0 20.0 ms reprogramming count n wec 1000 10000 ? times programming wait time after setting swe bit * 1 x 1 ? ? s wait time after setting psu bit * 1 y 50 ? ? s wait time after setting p bit z1 1 n 6 28 30 32 s * 1 * 4 z2 7 n 1000 198 200 202 s z3 additional- programming 8 10 12 s wait time after clearing p bit * 1 5 ? ? s wait time after clearing psu bit * 1 5 ? ? s wait time after setting pv bit * 1 4 ? ? s wait time after dummy write * 1 2 ? ? s wait time after clearing pv bit * 1 2 ? ? s wait time after clearing swe bit * 1 100 ? ? s maximum programming count * 1 * 4 * 5 n ? ? 1000 times
section 22 electrical characteristics rev. 3.00 sep. 10, 2007 page 433 of 528 rej09b0216-0300 values item symbol test condition min. typ. max. unit erasing wait time after setting swe bit * 1 x 1 ? ? s wait time after setting esu bit * 1 y 100 ? ? s wait time after setting e bit * 1 * 6 z 10 ? 100 ms wait time after clearing e bit * 1 10 ? ? s wait time after clearing esu bit * 1 10 ? ? s wait time after setting ev bit * 1 20 ? ? s wait time after dummy write * 1 2 ? ? s wait time after clearing ev bit * 1 4 ? ? s wait time after clearing swe bit * 1 100 ? ? s maximum erase count * 1 * 6 * 7 n ? ? 120 times notes: 1. make the time settings in accordance with the program/erase algorithms. 2. the programming time for 128 bytes. (indicates the total time for which the p bit in flash memory control register 1 (flmcr1) is set. the program-verify time is not included.) 3. the time required to erase one block. (indicates the time for which the e bit in flash memory control register 1 (flmcr1) is set. the erase-verify time is not included.) 4. programming time maximum value (t p (max.)) = wait time after p bit setting (z) maximum programming count (n) 5. set the maximum programming count (n) according to the actual set values of z1, z2, and z3 so that it does not exceed the programming time maximum value (t p (max.)). the wait time after setting p bit (z1, z2) should be changed as follows according to the value of the programming count (n). programming count (n) 1 n 6 z1 = 30 s 7 n 1000 z2 = 200 s 6. erase time maximum value (t e (max.)) = wait time a fter e bit setting (z) maximum erase count (n) 7. set the maximum erase count (n) according to the actual set value of (z) so that it does not exceed the erase time maximum value (t e (max.)).
section 22 electrical characteristics rev. 3.00 sep. 10, 2007 page 434 of 528 rej09b0216-0300 22.2.7 power-supply-voltage detection circuit characteristics table 22.9 power-supply-voltage detection circuit characteristics v ss = 0.0 v, t a = -20 to +75c/-40 to +85c, unless otherwise indicated. values item symbol test condition min. typ. max. unit power-supply falling detection voltage vint (d) lvdsel = 0 3.4 3.7 ? v power-supply rising detection voltage vint (u) lvdsel = 0 ? 4.0 4.4 v reset detection voltage 1 * 1 vreset1 lvdsel = 0 ? 2.3 2.6 v reset detection voltage 2 * 2 vreset2 lvdsel = 1 3.3 3.6 3.9 v lower-limit voltage of lvdr operation v lvdrmin 1.0 ? ? v notes: 1. this voltage should be used when the falling and rising voltage detection function is used. 2. select the low-voltage reset 2 when only the low-voltage detection reset is used. 22.2.8 lvdi external input voltage detection circuit characteristics table 22.10 lvdi external input volt age detection circuit characteristics vcc = 4.5 to 5.5 v, avcc = 4.5 to 5.5 v, v ss = 0.0 v, t a = -20 to +75c/-40 to +85c values item symbol test condition min. typ. max. unit extd/extu input detection voltage vexd 1.0 1.15 1.30 v extd/extu input voltage range vextd/vextu vextd > vextu ? 0.3 ? lower voltage of av cc + 0.3 or v cc + 0.3 v
section 22 electrical characteristics rev. 3.00 sep. 10, 2007 page 435 of 528 rej09b0216-0300 22.2.9 power-on reset circuit characteristics table 22.11 power-on rese t circuit characteristics v ss = 0.0 v, t a = -20 to +75c/-40 to +85c, unless otherwise indicated. values item symbol test condition min. typ. max unit pull-up resistance of res pin r res 100 150 ? k ? power-on reset start voltage * v por ? ? 100 mv note: * the power-supply voltage (vcc) must fall below vpor = 100 mv and then rise after charge of the res pin is removed completely. in order to remove charge of the res pin, it is recommended that the diode be placed in the vcc side. if the power-supply voltage (vcc) rises from the point over 100 mv, a power-on reset may not occur.
section 22 electrical characteristics rev. 3.00 sep. 10, 2007 page 436 of 528 rej09b0216-0300 22.3 electrical characteristics (f-ztat? 3.3-v version) 22.3.1 power supply voltage and operating ranges (1) power supply voltage and oscillation frequency range 4.0 16.0 3.0 3.6 v cc (v) osc (mhz) 32.768 3.0 3.6 v cc (v) w (khz) av cc = 3.0 to 3.6 v active mode sleep mode av cc = 3.0 to 3.6 v all operating modes
section 22 electrical characteristics rev. 3.00 sep. 10, 2007 page 437 of 528 rej09b0216-0300 (2) power supply voltage and operating frequency range 4.0 16.0 3.0 3.6 v cc (v) (mhz) 16.384 3.0 3.6 v cc (v) sub (khz) 8.192 4.096 78.125 2500 3.0 3.6 v cc (v) (khz) av cc = 3.0 to 3.6 v active mode sleep mode (when ma2 in syscr2 = 0) av cc = 3.0 to 3.6 v subactive mode subsleep mode av cc = 3.0 to 3.6 v active mode sleep mode (when ma2 in syscr2 = 1) (3) analog power supply voltage and a/d converter accuracy guaranteed range 4.0 16.0 3.0 3.6 av cc (v) (mhz) v cc = 3.0 to 3.6 v active mode sleep mode
section 22 electrical characteristics rev. 3.00 sep. 10, 2007 page 438 of 528 rej09b0216-0300 22.3.2 dc characteristics table 22.12 dc characteristics (1) v cc = 3.0 to 3.6 v, v ss = 0.0 v, t a = -20 to +75c/-40 to +85c, unless otherwise indicated. values item symbol applicable pins test condition min. typ. max. unit notes input high voltage v ih res , nmi , wkp0 to wkp5 , irq0 to irq3 , adtrg , tmib1, tmriv, v cc 0.9 ? v cc + 0.3 v tmciv, ftioa0 to ftiod0, ftioa1 to ftiod1, sck3, sck3_2, trgv rxd, rxd_2, scl, sda, p10 to p12, p14 to p17, p20 to p24, p30 to p37, v cc 0.8 ? v cc + 0.3 v p50 to p57, p60 to p67, p70 to p72 p74 to p76, p85 to p87, pc0, pc1 pb0 to pb7 av cc = 3.0 to 3.6 v av cc 0.8 ? av cc + 0.3 v osc1 v cc ? 0.3 ? v cc + 0.3 v input low voltage v il res , nmi , wkp0 to wkp5 , irq0 to irq3 , adtrg , tmib1, tmriv, ?0.3 ? v cc 0.1 v tmciv, ftioa0 to ftiod0, ftioa1 to ftiod1, sck3, sck3_2, trgv note: connect the test pin to vss.
section 22 electrical characteristics rev. 3.00 sep. 10, 2007 page 439 of 528 rej09b0216-0300 values item symbol applicable pins test condition min. typ. max. unit notes input low voltage v il rxd, rxd_2, scl, sda, p10 to p12, p14 to p17, p20 to p24, p30 to p37, ?0.3 ? v cc 0.2 v p50 to p57, p60 to p67, p70 to p72, p74 to p76, p85 to p87, pc0, pc1 pb0 to pb7 av cc = 3.0 to 3.6 v ?0.3 ? av cc 0.2 v osc1 ?0.3 ? 0.3 v output high voltage v oh p10 to p12, p14 to p17, p20 to p24, p30 to p37, ?i oh = 1.5 ma v cc ? 1.0 ? ? v p50 to p55, p60 to p67, p70 to p72, p74 to p76, p85 to p87, pc0, pc1 ?i oh = 0.1 ma v cc ? 0.5 ? ? p56, p57 ?i oh = 0.1 ma v cc ? 2.0 ? ? v output low voltage v ol p10 to p12, p14 to p17, p20 to p24, p30 to p37, i ol = 1.6 ma ? ? 0.6 v p50 to p57, p70 to p72, p74 to p76, p85 to p87 pc0, pc1 i ol = 0.4 ma ? ? 0.4 p60 to p67 i ol = 20.0 ma ? ? 1.5 v i ol = 10.0 ma ? ? 1.0 i ol = 1.6 ma ? ? 0.4 i ol = 0.4 ma ? ? 0.4 scl, sda i ol = 6.0 ma ? ? 0.6 i ol = 3.0 ma ? ? 0.4
section 22 electrical characteristics rev. 3.00 sep. 10, 2007 page 440 of 528 rej09b0216-0300 values item symbol applicable pins test condition min typ max unit notes input/ output leakage current | i il | osc1, tmib1, res , nmi , wkp0 to wkp5 , irq0 to irq3 , adtrg , trgv, tmriv, tmciv, ftioa0 to ftiod0, ftioa1 to ftiod1 rxd, sck3, rxd_2, sck3_2, scl, sda v in = 0.5 v to (v cc ? 0.5 v) ? ? 1.0 a p10 to p12, p14 to p17, p20 to p24, p30 to p37, p50 to p57, p60 to p67, p70 to p72, p74 to p76, p85 to p87, pc0, pc1 v in = 0.5 v to (v cc ? 0.5 v) ? ? 1.0 a pb0 to pb7 v in = 0.5 v to (av cc ? 0.5 v) ? ? 1.0 a pull-up mos current ?i p p10 to p12, p14 to p17, p50 to p55 v cc = 3.3 v, v in = 0.0 v ? 60.0 ? a input capaci- tance c in all input pins except power supply pins f = 4 mhz, v in = 0.0 v, t a = 25c ? ? 15.0 pf i ope1 v cc active mode 1 v cc = 3.3 v, f osc = 16 mhz ? 15.0 22.0 ma * active mode current consump- tion active mode 1 v cc = 3.3 v, f osc = 10 mhz ? 11.0 ? * reference value i ope2 v cc active mode 2 v cc = 3.3 v, f osc = 16 mhz ? 2.8 4.0 ma * active mode 2 v cc = 3.3 v, f osc = 10 mhz ? 2.5 ? * reference value
section 22 electrical characteristics rev. 3.00 sep. 10, 2007 page 441 of 528 rej09b0216-0300 values item symbol applicable pins test condition min. typ. max. unit notes i sleep1 v cc sleep mode 1 v cc = 3.3 v, f osc = 16 mhz ? 9.0 14.0 ma * sleep mode supply current sleep mode 1 v cc = 3.3 v, f osc = 10 mhz ? 6.5 ? * reference value i sleep2 v cc sleep mode 2 v cc = 3.3 v, f osc = 16 mhz ? 2.2 3.5 ma * sleep mode 2 v cc = 3.3 v, f osc = 10 mhz ? 2.0 ? * reference value i sub v cc v cc = 3.3 v 32-khz crystal resonator ( sub = w /2) ? 95.0 145.0 a * subactive mode supply current v cc = 3.3 v 32-khz crystal resonator ( sub = w /8) ? 85.0 ? * reference value subsleep mode supply current i subsp v cc v cc = 3.3 v 32-khz crystal resonator ( sub = w /2) ? 85.0 140.0 a * standby mode supply current i stby v cc 32-khz crystal resonator not used ? ? 135.0 a * ram data retention voltage v ram v cc 2.0 ? ? v
section 22 electrical characteristics rev. 3.00 sep. 10, 2007 page 442 of 528 rej09b0216-0300 note: * pin states during supply current measurement are given below (excluding current in the pull-up mos transistors and output buffers). mode res pin internal state other pins oscillator pins active mode 1 v cc operates v cc main clock: ceramic or crystal resonator, and on-chip oscillator active mode 2 operates ( osc /64) subclock: pin x1 = v ss sleep mode 1 v cc only timers operate v cc sleep mode 2 only timers operate ( osc /64) subactive mode v cc operates v cc main clock: ceramic or crystal resonator, and on-chip oscillator subsleep mode v cc only timers operate v cc subclock: crystal resonator standby mode v cc cpu and timers both stop v cc main clock: ceramic or crystal resonator, and on-chip oscillator subclock: pin x1 = v ss
section 22 electrical characteristics rev. 3.00 sep. 10, 2007 page 443 of 528 rej09b0216-0300 table 22.12 dc characteristics (2) v cc = 3.0 to 3.6 v, v ss = 0.0 v, t a = -20 to +75c/-40 to +85c, unless otherwise indicated. values item symbol applicable pins test condition min. typ. max. unit permissible output low current (per pin) i ol output pins except port 6, scl, and sda ? ? 2.0 ma port 6 ? ? 20.0 permissible output low current (total) i ol output pins except port 6, scl, and sda ? ? 40.0 ma port 6, scl, and sda ? ? 80.0 permissible output high current (per pin) ? ?i oh ? all output pins ? ? 5.0 ma permissible output high current (total) ? ? i oh ? all output pins ? ? 50.0 ma
section 22 electrical characteristics rev. 3.00 sep. 10, 2007 page 444 of 528 rej09b0216-0300 22.3.3 ac characteristics table 22.13 ac characteristics v cc = 3.0 to 3.6 v, v ss = 0.0 v, t a = -20 to +75c/-40 to +85c, unless otherwise indicated. values item symbol applicable pins test condition min. typ. max. unit reference figure system clock oscillation frequency f osc osc1, osc2 4.0 ? 16.0 mhz * 1 t cyc 1 ? 64 t osc * 2 system clock ( ) cycle time ? ? 12.8 s subclock oscillation frequency f w x1, x2 ? 32.768 ? khz watch clock ( w ) cycle time t w x1, x2 ? 30.5 ? s subclock ( sub ) cycle time t subcyc 2 ? 8 t w * 2 instruction cycle time 2 ? ? t cyc t subcyc oscillation stabilization time (crystal resonator) t rc osc1, osc2 ? ? 10.0 ms oscillation stabilization time (ceramic resonator) t rc osc1, osc2 ? ? 5.0 ms oscillation stabilization time (on-chip oscillator) t rc ? ? 500 s oscillation stabilization time t rcx x1, x2 ? ? 2.0 s external clock high width t cph osc1 23.8 ? ? ns figure 22.1 external clock low width t cpl osc1 23.8 ? ? ns external clock rise time t cpr osc1 ? ? 15.0 ns external clock fall time t cpf osc1 ? ? 15.0 ns
section 22 electrical characteristics rev. 3.00 sep. 10, 2007 page 445 of 528 rej09b0216-0300 values item symbol applicable pins test condition min. typ. max. unit reference figure res pin low width t rel res at power-on and in modes other than those below t rc ? ? ms figure 22.2 in active mode and sleep mode 2500 ? ? ns input pin high width t ih nmi , tmib1, irq0 to irq3 , wkp0 to wkp5 , tmciv, tmriv, trgv, adtrg , ftioa0 to ftiod0, ftioa1 to ftiod1 2 ? ? t cyc t subcyc figure 22.3 input pin low width t il nmi , tmib1, irq0 to irq3 , wkp0 to wkp5 , tmciv, tmriv, trgv, adtrg , ftioa0 to ftiod0, ftioa1 to ftiod1 2 ? ? t cyc t subcyc
section 22 electrical characteristics rev. 3.00 sep. 10, 2007 page 446 of 528 rej09b0216-0300 values item symbol applicable pins test condition min. typ. max. unit reference figure vcc = 3.3 v ta = 25 c fsel= 1 vclsel= 0 19.70 20.00 20.30 fsel = 1, ta = -20 to +75 c, vclsel = 0 19.40 20.00 20.60 fsel = 1, ta = -40 to 85 c, vclsel = 0 19.2 20.0 20.8 vcc = 3.3 v, ta = 25 c, fsel = 0, vclsel = 0 15.76 16.00 16.24 on-chip oscillator oscillation frequency f rc fsel = 0, ta = -20 to +75 c vclsel = 0 15.52 16.0 16.48 mhz fsel = 0, ta = -40 to +85c, vclsel = 0 15.36 16.0 16.64 notes: 1. when an external clock is input, the minimum frequency of the external clock oscillator is 4.0 mhz. 2. determined by ma2 to ma0, sa1, and sa0 in system control register 2 (syscr2).
section 22 electrical characteristics rev. 3.00 sep. 10, 2007 page 447 of 528 rej09b0216-0300 table 22.14 i 2 c bus interface timing v cc = 3.0 to 3.6 v, v ss = 0.0 v, t a = -20 to +75c/-40 to +85c, unless otherwise indicated. values item symbol test condition min. typ. max. unit reference figure scl input cycle time t scl 12t cyc + 600 ? ? ns figure 22.4 scl input high width t sclh 3t cyc + 300 ? ? ns scl input low width t scll 5t cyc + 300 ? ? ns scl and sda input fall time t sf ? ? 300 ns scl and sda input spike pulse removal time t sp ? ? 1t cyc ns sda input bus-free time t buf 5t cyc ? ? ns start condition input hold time t stah 3t cyc ? ? ns repeated start condition input setup time t stas 3t cyc ? ? ns setup time for stop condition input t stos 3t cyc ? ? ns data-input setup time t sdas 1t cyc +20 ? ? ns data-input hold time t sdah 0 ? ? ns capacitive load of scl and sda c b 0 ? 400 pf scl and sda output fall time t sf ? ? 250 ns
section 22 electrical characteristics rev. 3.00 sep. 10, 2007 page 448 of 528 rej09b0216-0300 table 22.15 serial communication interface (sci) timing v cc = 3.0 to 3.6 v, v ss = 0.0 v, t a = -20 to +75c/-40 to +85c, unless otherwise indicated. values item symbol applicable pins test condition min. typ. max. unit reference figure asynchro- nous t scyc sck3 4 ? ? t cyc figure 22.5 input clock cycle clock synchro- nous 6 ? ? input clock pulse width t sckw sck3 0.4 ? 0.6 t scyc transmit data delay time (clock synchronous) t txd txd ? ? 1 t cyc figure 22.6 receive data setup time (clock synchronous) t rxs rxd 50.0 ? ? ns receive data hold time (clock synchronous) t rxh rxd 50.0 ? ? ns
section 22 electrical characteristics rev. 3.00 sep. 10, 2007 page 449 of 528 rej09b0216-0300 22.3.4 a/d converter characteristics table 22.16 a/d converter characteristics v cc = 3.0 to 3.6 v, v ss = 0.0 v, t a = -20 to +75c/-40 to +85c, unless otherwise indicated. values item symbol applicable pins test condition min. typ. max. unit reference figure analog power supply voltage av cc av cc 3.0 v cc 3.6 v * 1 analog input voltage av in an0 to an7 v ss ? 0.3 ? av cc + 0.3 v analog power supply current ai ope av cc av cc = 3.6 v f osc = 16 mhz ? ? 2.0 ma ai stop1 av cc ? 50 ? a * 2 reference value ai stop2 av cc ? ? 5.0 a * 3 analog input capacitance c ain an0 to an7 ? ? 30.0 pf permissible signal source impedance r ain an0 to an7 ? ? 5.0 k ? resolution (data length) 10 10 10 bit conversion time (single mode) av cc = 3.0 to 3.6 v 134 ? ? t cyc nonlinearity error ? ? 7.5 lsb offset error ? ? 7.5 lsb full-scale error ? ? 7.5 lsb quantization error ? ? 0.5 lsb absolute accuracy ? ? 8.0 lsb notes: 1. set av cc = v cc when the a/d converter is not used. 2. ai stop1 is the current in active and sleep modes while the a/d converter is idle. 3. ai stop2 is the current at reset and in standby, subactive, and subsleep modes while the a/d converter is idle.
section 22 electrical characteristics rev. 3.00 sep. 10, 2007 page 450 of 528 rej09b0216-0300 22.3.5 watchdog timer characteristics table 22.17 watchdog timer characteristics v cc = 3.0 to 3.6 v, v ss = 0.0 v, t a = -20 to +75c/-40 to +85c, unless otherwise indicated. values item symbol applicable pins test condition min. typ. max. unit reference figure on-chip oscillator overflow time t ovf 0.2 0.4 ? s * note: * time until an internal reset is generated after the counter counts from 0 to 255 when the on-chip oscillator is selected
section 22 electrical characteristics rev. 3.00 sep. 10, 2007 page 451 of 528 rej09b0216-0300 22.3.6 flash memory characteristics table 22.18 flash memory characteristics v cc = 3.0 to 3.6 v, v ss = 0.0 v, t a = -20 to +75c/-40 to +85c, unless otherwise indicated. values item symbol test condition min. typ. max. unit programming time (per 128 bytes) * 1 * 2 * 4 t p ? 7.0 200.0 ms erase time (per block) * 1 * 3 * 6 t e ? 10.0 20.0 ms reprogramming count n wec 1000 10000 ? times programming wait time after setting swe bit * 1 x 1 ? ? s wait time after setting psu bit * 1 y 50 ? ? s wait time after setting p bit z1 1 n 6 28 30 32 s * 1 * 4 z2 7 n 1000 198 200 202 s z3 additional- programming 8 10 12 s wait time after clearing p bit * 1 5 ? ? s wait time after clearing psu bit * 1 5 ? ? s wait time after setting pv bit * 1 4 ? ? s wait time after dummy write * 1 2 ? ? s wait time after clearing pv bit * 1 2 ? ? s wait time after clearing swe bit * 1 100 ? ? s maximum programming count * 1 * 4 * 5 n ? ? 1000 times
section 22 electrical characteristics rev. 3.00 sep. 10, 2007 page 452 of 528 rej09b0216-0300 values item symbol test condition min. typ. max. unit erasing wait time after setting swe bit * 1 x 1 ? ? s wait time after setting esu bit * 1 y 100 ? ? s wait time after setting e bit * 1 * 6 z 10 ? 100 ms wait time after clearing e bit * 1 10 ? ? s wait time after clearing esu bit * 1 10 ? ? s wait time after setting ev bit * 1 20 ? ? s wait time after dummy write * 1 2 ? ? s wait time after clearing ev bit * 1 4 ? ? s wait time after clearing swe bit * 1 100 ? ? s maximum erase count * 1 * 6 * 7 n ? ? 120 times notes: 1. make the time settings in accordance with the program/erase algorithms. 2. the programming time for 128 bytes. (indicates the total time for which the p bit in flash memory control register 1 (flmcr1) is set. the program-verify time is not included.) 3. the time required to erase one block. (indicates the time for which the e bit in flash memory control register 1 (flmcr1) is set. the erase-verify time is not included.) 4. programming time maximum value (t p (max.)) = wait time after p bit setting (z) maximum programming count (n) 5. set the maximum programming count (n) according to the actual set values of z1, z2, and z3 so that it does not exceed the programming time maximum value (t p (max.)). the wait time after setting p bit (z1, z2) should be changed as follows according to the value of the programming count (n). programming count (n) 1 n 6 z1 = 30 s 7 n 1000 z2 = 200 s 6. erase time maximum value (t e (max.)) = wait time a fter e bit setting (z) maximum erase count (n) 7. set the maximum erase count (n) according to the actual set value of (z) so that it does not exceed the erase time maximum value (t e (max.)).
section 22 electrical characteristics rev. 3.00 sep. 10, 2007 page 453 of 528 rej09b0216-0300 22.3.7 power-supply-voltage detection circuit characteristics table 22.19 power-supply-voltage detection circuit characteristics v ss = 0.0 v, t a = -20 to +75c/-40 to +85c, unless otherwise indicated. values item symbol min. typ. max. unit power-supply falling detection voltage vint (d) 2.8 2.9 3.05 v power-supply rising detection voltage vint (u) 2.9 3.0 3.15 v reset detection voltage 1 * vreset1 ? 2.3 2.6 v lower-limit voltage of lvdr operation v lvdrmin 1.0 ? ? v note: * this voltage should be used when the falling and rising voltage detection function is used. 22.3.8 lvdi external input voltage detection circuit characteristics table 22.20 lvdi external input volt age detection circuit characteristics vcc = 3.0 to 3.6 v, avcc = 3.0 to 3.6 v, v ss = 0.0 v, t a = -20 to +75c/-40 to +85c values item symbol test condition min. typ. max. unit extd/extu input detection voltage vexd 0.95 1.15 1.35 v extd/extu input voltage range vextd/vextu vextd > vextu ? 0.3 ? lower voltage of av cc + 0.3 or v cc + 0.3 v
section 22 electrical characteristics rev. 3.00 sep. 10, 2007 page 454 of 528 rej09b0216-0300 22.3.9 power-on reset circuit characteristics table 22.21 power-on rese t circuit characteristics v ss = 0.0 v, t a = -20 to +75c/-40 to +85c, unless otherwise indicated. values item symbol test condition min. typ. max unit pull-up resistance of res pin r res 100 150 ? k ? power-on reset start voltage * v por ? ? 100 mv note: * the power-supply voltage (vcc) must fall below vpor = 100 mv and then rise after charge of the res pin is removed completely. in order to remove charge of the res pin, it is recommended that the diode be placed in the vcc side. if the power-supply voltage (vcc) rises from the point over 100 mv, a power-on reset may not occur.
section 22 electrical characteristics rev. 3.00 sep. 10, 2007 page 455 of 528 rej09b0216-0300 22.4 operation timing t osc v ih v il t cph t cpl t cpr osc1 t cpf figure 22.1 system clock input timing t rel v il res t rel v il v cc 0.7 v cc osc1 figure 22.2 res low width timing v ih v il t il nmi irq0 to irq3 wkp0 to wkp5 adtrg ftioa0 to ftiod0, ftioa1 to ftiod1, tmciv, tmriv trgv t ih figure 22.3 input timing
section 22 electrical characteristics rev. 3.00 sep. 10, 2007 page 456 of 528 rej09b0216-0300 scl v ih v il t stah t buf p * s * t sf t sr t scl t sdah t sclh t scll sda sr * t stas t sp t stos t sdas p * note: * s, p, and sr represent the following: s: start condition p: stop condition sr: retransmission start condition figure 22.4 i 2 c bus interface input/output timing t scyc t sckw sck3 figure 22.5 sck3 input clock timing
section 22 electrical characteristics rev. 3.00 sep. 10, 2007 page 457 of 528 rej09b0216-0300 t scyc t txd t rxs t rxh v oh v or v ih oh v or v il ol * * * v ol * sck3 txd (transmit data) rxd (receive data) note: * output timing reference levels output high: output low: load conditions are shown in figure 22.7. v = 2.0 v v = 0.8 v oh ol figure 22.6 sci input/output timing in clock synchronous mode
section 22 electrical characteristics rev. 3.00 sep. 10, 2007 page 458 of 528 rej09b0216-0300 22.5 output load condition v cc 2.4 k ? 12 k ? 30 pf lsi output pin figure 22.7 output load circuit
appendix rev. 3.00 sep. 10, 2007 page 459 of 528 rej09b0216-0300 appendix a instruction set a.1 instruction list condition code symbol description rd general destination register rs general source register rn general register erd general destination register (address register or 32-bit register) ers general source register (address register or 32-bit register) ern general register (32-bit register) (ead) destination operand (eas) source operand pc program counter sp stack pointer ccr condition-code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr disp displacement transfer from the operand on the left to the operand on the right, or transition from the state on the left to the state on the right + addition of the operands on both sides ? subtraction of the operand on the right from the operand on the left multiplication of the operands on both sides division of the operand on the left by the operand on the right logical and of the operands on both sides logical or of the operands on both sides logical exclusive or of the operands on both sides ? not (logical complement) ( ), < > contents of operand note: general registers include 8-bit registers (r0h to r7h and r0l to r7l) and 16-bit registers (r0 to r7 and e0 to e7).
appendix rev. 3.00 sep. 10, 2007 page 460 of 528 rej09b0216-0300 condition code notation (cont) symbol description ? changed according to execution result * undetermined (no guaranteed value) 0 cleared to 0 1 set to 1 ? not affected by execution of the instruction ? varies depending on conditions, described in notes
appendix rev. 3.00 sep. 10, 2007 page 461 of 528 rej09b0216-0300 table a.1 instruction set 1. data transfer instructions mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? mov.b #xx:8, rd mov.b rs, rd mov.b @ers, rd mov.b @(d:16, ers), rd mov.b @(d:24, ers), rd mov.b @ers+, rd mov.b @aa:8, rd mov.b @aa:16, rd mov.b @aa:24, rd mov.b rs, @erd mov.b rs, @(d:16, erd) mov.b rs, @(d:24, erd) mov.b rs, @?erd mov.b rs, @aa:8 mov.b rs, @aa:16 mov.b rs, @aa:24 mov.w #xx:16, rd mov.w rs, rd mov.w @ers, rd mov.w @(d:16, ers), rd mov.w @(d:24, ers), rd mov.w @ers+, rd mov.w @aa:16, rd mov.w @aa:24, rd mov.w rs, @erd mov.w rs, @(d:16, erd) mov.w rs, @(d:24, erd) operation #xx:8 rd8 rs8 rd8 @ers rd8 @(d:16, ers) rd8 @(d:24, ers) rd8 @ers rd8 ers32+1 ers32 @aa:8 rd8 @aa:16 rd8 @aa:24 rd8 rs8 @erd rs8 @(d:16, erd) rs8 @(d:24, erd) erd32?1 erd32 rs8 @erd rs8 @aa:8 rs8 @aa:16 rs8 @aa:24 #xx:16 rd16 rs16 rd16 @ers rd16 @(d:16, ers) rd16 @(d:24, ers) rd16 @ers rd16 ers32+2 @erd32 @aa:16 rd16 @aa:24 rd16 rs16 @erd rs16 @(d:16, erd) rs16 @(d:24, erd) b b b b b b b b b b b b b b b b w w w w w w w w w w w 2 4 2 2 2 2 2 2 4 8 4 8 4 8 4 8 2 2 2 2 4 6 2 4 6 4 6 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 4 6 10 6 4 6 8 4 6 10 6 4 6 8 4 2 4 6 10 6 6 8 4 6 10 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? mov
appendix rev. 3.00 sep. 10, 2007 page 462 of 528 rej09b0216-0300 mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? mov.w rs, @?erd mov.w rs, @aa:16 mov.w rs, @aa:24 mov.l #xx:32, rd mov.l ers, erd mov.l @ers, erd mov.l @(d:16, ers), erd mov.l @(d:24, ers), erd mov.l @ers+, erd mov.l @aa:16, erd mov.l @aa:24, erd mov.l ers, @erd mov.l ers, @(d:16, erd) mov.l ers, @(d:24, erd) mov.l ers, @?erd mov.l ers, @aa:16 mov.l ers, @aa:24 pop.w rn pop.l ern push.w rn push.l ern movfpe @aa:16, rd movtpe rs, @aa:16 operation erd32?2 erd32 rs16 @erd rs16 @aa:16 rs16 @aa:24 #xx:32 rd32 ers32 erd32 @ers erd32 @(d:16, ers) erd32 @(d:24, ers) erd32 @ers erd32 ers32+4 ers32 @aa:16 erd32 @aa:24 erd32 ers32 @erd ers32 @(d:16, erd) ers32 @(d:24, erd) erd32?4 erd32 ers32 @erd ers32 @aa:16 ers32 @aa:24 @sp rn16 sp+2 sp @sp ern32 sp+4 sp sp?2 sp rn16 @sp sp?4 sp ern32 @sp cannot be used in this lsi cannot be used in this lsi w w w l l l l l l l l l l l l l l w l w l b b 6 2 4 4 6 10 6 10 2 4 4 4 6 6 8 6 8 4 4 2 4 2 4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 6 8 6 2 8 10 14 10 10 12 8 10 14 10 10 12 6 10 6 10 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? cannot be used in this lsi cannot be used in this lsi mov pop push movfpe movtpe
appendix rev. 3.00 sep. 10, 2007 page 463 of 528 rej09b0216-0300 2. arithmetic instructions mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? add.b #xx:8, rd add.b rs, rd add.w #xx:16, rd add.w rs, rd add.l #xx:32, erd add.l ers, erd addx.b #xx:8, rd addx.b rs, rd adds.l #1, erd adds.l #2, erd adds.l #4, erd inc.b rd inc.w #1, rd inc.w #2, rd inc.l #1, erd inc.l #2, erd daa rd sub.b rs, rd sub.w #xx:16, rd sub.w rs, rd sub.l #xx:32, erd sub.l ers, erd subx.b #xx:8, rd subx.b rs, rd subs.l #1, erd subs.l #2, erd subs.l #4, erd dec.b rd dec.w #1, rd dec.w #2, rd operation rd8+#xx:8 rd8 rd8+rs8 rd8 rd16+#xx:16 rd16 rd16+rs16 rd16 erd32+#xx:32 erd32 erd32+ers32 erd32 rd8+#xx:8 +c rd8 rd8+rs8 +c rd8 erd32+1 erd32 erd32+2 erd32 erd32+4 erd32 rd8+1 rd8 rd16+1 rd16 rd16+2 rd16 erd32+1 erd32 erd32+2 erd32 rd8 decimal adjust rd8 rd8?rs8 rd8 rd16?#xx:16 rd16 rd16?rs16 rd16 erd32?#xx:32 erd32 erd32?ers32 erd32 rd8?#xx:8?c rd8 rd8?rs8?c rd8 erd32?1 erd32 erd32?2 erd32 erd32?4 erd32 rd8?1 rd8 rd16?1 rd16 rd16?2 rd16 b b w w l l b b l l l b w w l l b b w w l l b b l l l b w w 2 4 6 2 4 6 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (1) (1) (2) (2) ? ? ? ? ? ? ? ? * (1) (1) (2) (2) ? ? ? ? ? ? 2 2 4 2 6 2 2 2 2 2 2 2 2 2 2 2 2 2 4 2 6 2 2 2 2 2 2 2 2 2 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (3) (3) ? ? ? (3) (3) ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? * ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? add addx adds inc daa sub subx subs dec
appendix rev. 3.00 sep. 10, 2007 page 464 of 528 rej09b0216-0300 mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? dec.l #1, erd dec.l #2, erd das.rd mulxu. b rs, rd mulxu. w rs, erd mulxs. b rs, rd mulxs. w rs, erd divxu. b rs, rd divxu. w rs, erd divxs. b rs, rd divxs. w rs, erd cmp.b #xx:8, rd cmp.b rs, rd cmp.w #xx:16, rd cmp.w rs, rd cmp.l #xx:32, erd cmp.l ers, erd operation erd32?1 erd32 erd32?2 erd32 rd8 decimal adjust rd8 rd8 rs8 rd16 (unsigned multiplication) rd16 rs16 erd32 (unsigned multiplication) rd8 rs8 rd16 (signed multiplication) rd16 rs16 erd32 (signed multiplication) rd16 rs8 rd16 (rdh: remainder, rdl: quotient) (unsigned division) erd32 rs16 erd32 (ed: remainder, rd: quotient) (unsigned division) rd16 rs8 rd16 (rdh: remainder, rdl: quotient) (signed division) erd32 rs16 erd32 (ed: remainder, rd: quotient) (signed division) rd8?#xx:8 rd8?rs8 rd16?#xx:16 rd16?rs16 erd32?#xx:32 erd32?ers32 l l b b w b w b w b w b b w w l l 2 4 6 2 2 2 2 2 4 4 2 2 4 4 2 2 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 2 2 14 22 16 24 14 22 16 24 2 2 4 2 4 2 normal advanced ? ? ? ? ? * ? ? ? ? ? ? ? ? (1) (1) (2) (2) ? ? ? ? ? * ? ? ? ? ? ? ? ? ? ? (7) (7) (7) (7) ? ? (6) (6) (8) (8) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? dec das mulxu mulxs divxu divxs cmp
appendix rev. 3.00 sep. 10, 2007 page 465 of 528 rej09b0216-0300 mnemonic operation operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? neg.b rd neg.w rd neg.l erd extu.w rd extu.l erd exts.w rd exts.l erd 0?rd8 rd8 0?rd16 rd16 0?erd32 erd32 0 ( of rd16) 0 ( of erd32) ( of rd16) ( of rd16) ( of erd32) ( of erd32) b w l w l w l 2 2 2 2 2 2 2 ? ? ? ? ? ? ? ? ? ? ? 2 2 2 2 2 2 2 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 ? ? ? ? ? ? ? ? ? ? neg extu exts
appendix rev. 3.00 sep. 10, 2007 page 466 of 528 rej09b0216-0300 3. logic instructions mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? and.b #xx:8, rd and.b rs, rd and.w #xx:16, rd and.w rs, rd and.l #xx:32, erd and.l ers, erd or.b #xx:8, rd or.b rs, rd or.w #xx:16, rd or.w rs, rd or.l #xx:32, erd or.l ers, erd xor.b #xx:8, rd xor.b rs, rd xor.w #xx:16, rd xor.w rs, rd xor.l #xx:32, erd xor.l ers, erd not.b rd not.w rd not.l erd operation rd8 #xx:8 rd8 rd8 rs8 rd8 rd16 #xx:16 rd16 rd16 rs16 rd16 erd32 #xx:32 erd32 erd32 ers32 erd32 rd8 ? #xx:8 rd8 rd8 ? rs8 rd8 rd16 ? #xx:16 rd16 rd16 ? rs16 rd16 erd32 ? #xx:32 erd32 erd32 ? ers32 erd32 rd8 #xx:8 rd8 rd8 rs8 rd8 rd16 #xx:16 rd16 rd16 rs16 rd16 erd32 #xx:32 erd32 erd32 ers32 erd32 ? rd8 rd8 ? rd16 rd16 ? rd32 rd32 b b w w l l b b w w l l b b w w l l b w l 2 4 6 2 4 6 2 4 6 2 2 4 2 2 4 2 2 4 2 2 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 4 2 6 4 2 2 4 2 6 4 2 2 4 2 6 4 2 2 2 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? and or xor not
appendix rev. 3.00 sep. 10, 2007 page 467 of 528 rej09b0216-0300 4. shift instructions mnemonic operand size no. of states * 1 condition code ihnzvc shal.b rd shal.w rd shal.l erd shar.b rd shar.w rd shar.l erd shll.b rd shll.w rd shll.l erd shlr.b rd shlr.w rd shlr.l erd rotxl.b rd rotxl.w rd rotxl.l erd rotxr.b rd rotxr.w rd rotxr.l erd rotl.b rd rotl.w rd rotl.l erd rotr.b rd rotr.w rd rotr.l erd b w l b w l b w l b w l b w l b w l b w l b w l ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 normal advanced ? ? ? ? addressing mode and instruction length (bytes) #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 operation msb lsb 0 c msb lsb 0 c c msb lsb 0c msb lsb c msb lsb c msb lsb c msb lsb c msb lsb ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? shal shar shll shlr rotxl rotxr rotl rotr
appendix rev. 3.00 sep. 10, 2007 page 468 of 528 rej09b0216-0300 5. bit-manipulation instructions mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? bset #xx:3, rd bset #xx:3, @erd bset #xx:3, @aa:8 bset rn, rd bset rn, @erd bset rn, @aa:8 bclr #xx:3, rd bclr #xx:3, @erd bclr #xx:3, @aa:8 bclr rn, rd bclr rn, @erd bclr rn, @aa:8 bnot #xx:3, rd bnot #xx:3, @erd bnot #xx:3, @aa:8 bnot rn, rd bnot rn, @erd bnot rn, @aa:8 btst #xx:3, rd btst #xx:3, @erd btst #xx:3, @aa:8 btst rn, rd btst rn, @erd btst rn, @aa:8 bld #xx:3, rd operation (#xx:3 of rd8) 1 (#xx:3 of @erd) 1 (#xx:3 of @aa:8) 1 (rn8 of rd8) 1 (rn8 of @erd) 1 (rn8 of @aa:8) 1 (#xx:3 of rd8) 0 (#xx:3 of @erd) 0 (#xx:3 of @aa:8) 0 (rn8 of rd8) 0 (rn8 of @erd) 0 (rn8 of @aa:8) 0 (#xx:3 of rd8) ? (#xx:3 of rd8) (#xx:3 of @erd) ? (#xx:3 of @erd) (#xx:3 of @aa:8) ? (#xx:3 of @aa:8) (rn8 of rd8) ? (rn8 of rd8) (rn8 of @erd) ? (rn8 of @erd) (rn8 of @aa:8) ? (rn8 of @aa:8) ? (#xx:3 of rd8) z ? (#xx:3 of @erd) z ? (#xx:3 of @aa:8) z ? (rn8 of @rd8) z ? (rn8 of @erd) z ? (rn8 of @aa:8) z (#xx:3 of rd8) c b b b b b b b b b b b b b b b b b b b b b b b b b 2 2 2 2 2 2 2 2 2 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 8 8 2 8 8 2 8 8 2 8 8 2 8 8 2 8 8 2 6 6 2 6 6 2 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bset bclr bnot btst bld
appendix rev. 3.00 sep. 10, 2007 page 469 of 528 rej09b0216-0300 mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? bld #xx:3, @erd bld #xx:3, @aa:8 bild #xx:3, rd bild #xx:3, @erd bild #xx:3, @aa:8 bst #xx:3, rd bst #xx:3, @erd bst #xx:3, @aa:8 bist #xx:3, rd bist #xx:3, @erd bist #xx:3, @aa:8 band #xx:3, rd band #xx:3, @erd band #xx:3, @aa:8 biand #xx:3, rd biand #xx:3, @erd biand #xx:3, @aa:8 bor #xx:3, rd bor #xx:3, @erd bor #xx:3, @aa:8 bior #xx:3, rd bior #xx:3, @erd bior #xx:3, @aa:8 bxor #xx:3, rd bxor #xx:3, @erd bxor #xx:3, @aa:8 bixor #xx:3, rd bixor #xx:3, @erd bixor #xx:3, @aa:8 operation (#xx:3 of @erd) c (#xx:3 of @aa:8) c ? (#xx:3 of rd8) c ? (#xx:3 of @erd) c ? (#xx:3 of @aa:8) c c (#xx:3 of rd8) c (#xx:3 of @erd24) c (#xx:3 of @aa:8) ? c (#xx:3 of rd8) ? c (#xx:3 of @erd24) ? c (#xx:3 of @aa:8) c (#xx:3 of rd8) c c (#xx:3 of @erd24) c c (#xx:3 of @aa:8) c c ? (#xx:3 of rd8) c c ? (#xx:3 of @erd24) c c ? (#xx:3 of @aa:8) c c (#xx:3 of rd8) c c (#xx:3 of @erd24) c c (#xx:3 of @aa:8) c c ? (#xx:3 of rd8) c c ? (#xx:3 of @erd24) c c ? (#xx:3 of @aa:8) c c (#xx:3 of rd8) c c (#xx:3 of @erd24) c c (#xx:3 of @aa:8) c c ? (#xx:3 of rd8) c c ? (#xx:3 of @erd24) c c ? (#xx:3 of @aa:8) c b b b b b b b b b b b b b b b b b b b b b b b b b b b b b 2 2 2 2 2 2 2 2 2 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 6 6 2 6 6 2 8 8 2 8 8 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bld bild bist bst band biand bor bior bxor bixor
appendix rev. 3.00 sep. 10, 2007 page 470 of 528 rej09b0216-0300 6. branching instructions ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? mnemonic operand size no. of states * 1 condition code ihnzvc bra d:8 (bt d:8) bra d:16 (bt d:16) brn d:8 (bf d:8) brn d:16 (bf d:16) bhi d:8 bhi d:16 bls d:8 bls d:16 bcc d:8 (bhs d:8) bcc d:16 (bhs d:16) bcs d:8 (blo d:8) bcs d:16 (blo d:16) bne d:8 bne d:16 beq d:8 beq d:16 bvc d:8 bvc d:16 bvs d:8 bvs d:16 bpl d:8 bpl d:16 bmi d:8 bmi d:16 bge d:8 bge d:16 blt d:8 blt d:16 bgt d:8 bgt d:16 ble d:8 ble d:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 normal advanced addressing mode and instruction length (bytes) #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 operation always never c z = 0 c z = 1 c = 0 c = 1 z = 0 z = 1 v = 0 v = 1 n = 0 n = 1 n v = 0 n v = 1 z (n v) = 0 z (n v) = 1 if condition is true then pc pc+d else next; branch condition bcc
appendix rev. 3.00 sep. 10, 2007 page 471 of 528 rej09b0216-0300 mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? jmp @ern jmp @aa:24 jmp @@aa:8 bsr d:8 bsr d:16 jsr @ern jsr @aa:24 jsr @@aa:8 rts operation pc ern pc aa:24 pc @aa:8 pc @?sp pc pc+d:8 pc @?sp pc pc+d:16 pc @?sp pc ern pc @?sp pc aa:24 pc @?sp pc @aa:8 pc @sp+ ? ? ? ? ? ? ? ? ? 2 2 4 4 2 4 2 2 2 ? ? ? ? ? ? ? ? ? 4 6 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 8 6 8 6 8 8 8 10 8 10 8 10 12 10 jmp bsr jsr rts
appendix rev. 3.00 sep. 10, 2007 page 472 of 528 rej09b0216-0300 7. system control instructions mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? trapa #x:2 rte sleep ldc #xx:8, ccr ldc rs, ccr ldc @ers, ccr ldc @(d:16, ers), ccr ldc @(d:24, ers), ccr ldc @ers+, ccr ldc @aa:16, ccr ldc @aa:24, ccr stc ccr, rd stc ccr, @erd stc ccr, @(d:16, erd) stc ccr, @(d:24, erd) stc ccr, @?erd stc ccr, @aa:16 stc ccr, @aa:24 andc #xx:8, ccr orc #xx:8, ccr xorc #xx:8, ccr nop operation pc @?sp ccr @?sp pc ccr @sp+ pc @sp+ transition to power- down state #xx:8 ccr rs8 ccr @ers ccr @(d:16, ers) ccr @(d:24, ers) ccr @ers ccr ers32+2 ers32 @aa:16 ccr @aa:24 ccr ccr rd8 ccr @erd ccr @(d:16, erd) ccr @(d:24, erd) erd32?2 erd32 ccr @erd ccr @aa:16 ccr @aa:24 ccr #xx:8 ccr ccr #xx:8 ccr ccr #xx:8 ccr pc pc+2 ? ? ? b b w w w w w w b w w w w w w b b b ? 2 2 2 2 2 2 4 4 6 10 6 10 4 4 6 8 6 8 2 2 1 ? ? ? ? ? ? ? ? ? 10 2 2 2 6 8 12 8 8 10 2 6 8 12 8 8 10 2 2 2 2 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 14 16 trapa rte sleep ldc stc andc orc xorc nop
appendix rev. 3.00 sep. 10, 2007 page 473 of 528 rej09b0216-0300 8. block transfer instructions mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? eepmov. b eepmov. w operation if r4l 0 then repeat @r5 @r6 r5+1 r5 r6+1 r6 r4l?1 r4l until r4l=0 else next if r4 0 then repeat @r5 @r6 r5+1 r5 r6+1 r6 r4?1 r4 until r4=0 else next ? ? 4 4 ? ? 8+ 4n * 2 normal advanced ? ? ? ? ? ? ? ? ? ?8+ 4n * 2 eepmov notes: 1. the number of states in cases where the instruction code and its operands are located in on-chip memory is shown here. for other cases see appendix a.3, number of execution states. 2. n is the value set in register r4l or r4. (1) set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0. (2) set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0. (3) retains its previous value when the result is zero; otherwise cleared to 0. (4) set to 1 when the adjustment produces a carry; otherwise retains its previous value. (5) the number of states required for execution of an instruction that transfers data in synchronization with the e clock is variable. (6) set to 1 when the divisor is negative; otherwise cleared to 0. (7) set to 1 when the divisor is zero; otherwise cleared to 0. (8) set to 1 when the quotient is negative; otherwise cleared to 0.
appendix rev. 3.00 sep. 10, 2007 page 474 of 528 rej09b0216-0300 a.2 operation code map table a.2 operation code map (1) ah al 0123456789abcdef 0 1 2 3 4 5 6 7 8 9 a b c d e f nop bra mulxu bset brn divxu bnot stc bhi mulxu bclr ldc bls divxu btst orc or.b bcc rts or xorc xor.b bcs bsr xor bor bior bxor bixor band biand andc and.b bne rte and ldc beq trapa bld bild bst bist bvc mov bpl jmp bmi eepmov addx subx bgt jsr ble mov add addx cmp subx or xor and mov instruction when most significant bit of bh is 0. instruction when most significant bit of bh is 1. instruction code: table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) bvs blt bge bsr table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (3) 1st byte 2nd byte ah bh al bl add sub mov cmp mov.b
appendix rev. 3.00 sep. 10, 2007 page 475 of 528 rej09b0216-0300 table a.2 operation code map (2) ah al bh 0123456789abcdef 01 0a 0b 0f 10 11 12 13 17 1a 1b 1f 58 79 7a mov inc adds daa dec subs das bra mov mov bhi cmp cmp ldc/stc bcc or or bpl bgt instruction code: bvs sleep bvc bge table a.2 (3) table a.2 (3) table a.2 (3) add mov sub cmp bne and and inc extu dec beq inc extu dec bcs xor xor shll shlr rotxl rotxr not bls sub sub brn add add inc exts dec blt inc exts dec ble shal shar rotl rotr neg bmi 1st byte 2nd byte ah bh al bl sub adds shll shlr rotxl rotxr not shal shar rotl rotr neg
appendix rev. 3.00 sep. 10, 2007 page 476 of 528 rej09b0216-0300 table a.2 operation code map (3) ah albh blch cl 0123456789abcdef 01406 01c05 01d05 01f06 7cr06 7cr07 7dr06 7dr07 7eaa6 7eaa7 7faa6 7faa7 mulxs bset bset bset bset divxs bnot bnot bnot bnot mulxs bclr bclr bclr bclr divxs btst btst btst btst or xor bor bior bxor bixor band biand and bld bild bst bist instruction when most significant bit of dh is 0. instruction when most significant bit of dh is 1. instruction code: * * * * * * * * 1 1 1 1 2 2 2 2 bor bior bxor bixor band biand bld bild bst bist notes: 1. 2. r is the register designation field. aa is the absolute address field. 1st byte 2nd byte ah bh al bl 3rd byte ch dh cl dl 4th byte ldc stc ldc ldc ldc stc stc stc
appendix rev. 3.00 sep. 10, 2007 page 477 of 528 rej09b0216-0300 a.3 number of ex ecution states the status of execution for each instruction of the h8/300h cpu and the method of calculating the number of states required for instruction execution are shown below. table a.4 shows the number of cycles of each type occurring in each in struction, such as instruction fetch and data read/write. table a.3 shows the number of states required for each cycle. the total number of states required for execution of an instruction can be calculated by the following expression: execution states = i s i + j s j + k s k + l s l + m s m + n s n examples: when instruction is fetched from on-c hip rom, and an on-chip ram is accessed. bset #0, @ff00 from table a.4: i = l = 2, j = k = m = n= 0 from table a.3: s i = 2, s l = 2 number of states required for execution = 2 2 + 2 2 = 8 when instruction is fetched from on-chip rom, branch address is read from on-chip rom, and on-chip ram is used for stack area. jsr @@ 30 from table a.4: i = 2, j = k = 1, l = m = n = 0 from table a.3: s i = s j = s k = 2 number of states required for execution = 2 2 + 1 2+ 1 2 = 8
appendix rev. 3.00 sep. 10, 2007 page 478 of 528 rej09b0216-0300 table a.3 number of cycles in each instruction access location execution status (instruction cycle) on-chip memory on-chip peripheral module instruction fetch s i 2 ? branch address read s j stack operation s k byte data access s l 2 or 3 * word data access s m 2 or 3 * internal operation s n 1 note: * depends on which on-chip peripheral module is accessed. see section 21.1, register addresses (address order).
appendix rev. 3.00 sep. 10, 2007 page 479 of 528 rej09b0216-0300 table a.4 number of cycles in each instruction instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n add add.b #xx:8, rd add.b rs, rd add.w #xx:16, rd add.w rs, rd add.l #xx:32, erd add.l ers, erd 1 1 2 1 3 1 adds adds #1/2/4, erd 1 addx addx #xx:8, rd addx rs, rd 1 1 and and.b #xx:8, rd and.b rs, rd and.w #xx:16, rd and.w rs, rd and.l #xx:32, erd and.l ers, erd 1 1 2 1 3 2 andc andc #xx:8, ccr 1 band band #xx:3, rd band #xx:3, @erd band #xx:3, @aa:8 1 2 2 1 1
appendix rev. 3.00 sep. 10, 2007 page 480 of 528 rej09b0216-0300 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n bcc bra d:8 (bt d:8) brn d:8 (bf d:8) bhi d:8 bls d:8 bcc d:8 (bhs d:8) bcs d:8 (blo d:8) bne d:8 beq d:8 bvc d:8 bvs d:8 bpl d:8 bmi d:8 bge d:8 2 2 2 2 2 2 2 2 2 2 2 2 2 bcc blt d:8 bgt d:8 ble d:8 bra d:16(bt d:16) brn d:16(bf d:16) bhi d:16 bls d:16 bcc d:16(bhs d:16) bcs d:16(blo d:16) bne d:16 beq d:16 bvc d:16 bvs d:16 bpl d:16 bmi d:16 bge d:16 blt d:16 bgt d:16 ble d:16 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
appendix rev. 3.00 sep. 10, 2007 page 481 of 528 rej09b0216-0300 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n bclr bclr #xx:3, rd bclr #xx:3, @erd bclr #xx:3, @aa:8 bclr rn, rd bclr rn, @erd bclr rn, @aa:8 1 2 2 1 2 2 2 2 2 2 biand biand #xx:3, rd biand #xx:3, @erd biand #xx:3, @aa:8 1 2 2 1 1 bild bild #xx:3, rd bild #xx:3, @erd bild #xx:3, @aa:8 1 2 2 1 1 bior bior #xx:8, rd bior #xx:8, @erd bior #xx:8, @aa:8 1 2 2 1 1 bist bist #xx:3, rd bist #xx:3, @erd bist #xx:3, @aa:8 1 2 2 2 2 bixor bixor #xx:3, rd bixor #xx:3, @erd bixor #xx:3, @aa:8 1 2 2 1 1 bld bld #xx:3, rd bld #xx:3, @erd bld #xx:3, @aa:8 1 2 2 1 1 bnot bnot #xx:3, rd bnot #xx:3, @erd bnot #xx:3, @aa:8 bnot rn, rd bnot rn, @erd bnot rn, @aa:8 1 2 2 1 2 2 2 2 2 2
appendix rev. 3.00 sep. 10, 2007 page 482 of 528 rej09b0216-0300 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n bor bor #xx:3, rd bor #xx:3, @erd bor #xx:3, @aa:8 1 2 2 1 1 bset bset #xx:3, rd bset #xx:3, @erd bset #xx:3, @aa:8 bset rn, rd bset rn, @erd bset rn, @aa:8 1 2 2 1 2 2 2 2 2 2 bsr bsr d:8 bsr d:16 2 2 1 1 2 bst bst #xx:3, rd bst #xx:3, @erd bst #xx:3, @aa:8 1 2 2 2 2 btst btst #xx:3, rd btst #xx:3, @erd btst #xx:3, @aa:8 btst rn, rd btst rn, @erd btst rn, @aa:8 1 2 2 1 2 2 1 1 1 1 bxor bxor #xx:3, rd bxor #xx:3, @erd bxor #xx:3, @aa:8 1 2 2 1 1 cmp cmp.b #xx:8, rd cmp.b rs, rd cmp.w #xx:16, rd cmp.w rs, rd cmp.l #xx:32, erd cmp.l ers, erd 1 1 2 1 3 1 daa daa rd 1 das das rd 1
appendix rev. 3.00 sep. 10, 2007 page 483 of 528 rej09b0216-0300 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n dec dec.b rd dec.w #1/2, rd dec.l #1/2, erd 1 1 1 duvxs divxs.b rs, rd divxs.w rs, erd 2 2 12 20 divxu divxu.b rs, rd divxu.w rs, erd 1 1 12 20 eepmov eepmov.b eepmov.w 2 2 2n+2 * 1 2n+2 * 1 exts exts.w rd exts.l erd 1 1 extu extu.w rd extu.l erd 1 1 inc inc.b rd inc.w #1/2, rd inc.l #1/2, erd 1 1 1 jmp jmp @ern jmp @aa:24 jmp @@aa:8 2 2 2 1 2 2 jsr jsr @ern jsr @aa:24 jsr @@aa:8 2 2 2 1 1 1 1 2 ldc ldc #xx:8, ccr ldc rs, ccr ldc@ers, ccr ldc@(d:16, ers), ccr ldc@(d:24,ers), ccr ldc@ers+, ccr ldc@aa:16, ccr ldc@aa:24, ccr 1 1 2 3 5 2 3 4 1 1 1 1 1 1 2
appendix rev. 3.00 sep. 10, 2007 page 484 of 528 rej09b0216-0300 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n mov mov.b #xx:8, rd mov.b rs, rd mov.b @ers, rd mov.b @(d:16, ers), rd mov.b @(d:24, ers), rd mov.b @ers+, rd mov.b @aa:8, rd mov.b @aa:16, rd mov.b @aa:24, rd mov.b rs, @erd mov.b rs, @(d:16, erd) mov.b rs, @(d:24, erd) mov.b rs, @-erd mov.b rs, @aa:8 1 1 1 2 4 1 1 2 3 1 2 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 mov mov.b rs, @aa:16 mov.b rs, @aa:24 mov.w #xx:16, rd mov.w rs, rd mov.w @ers, rd mov.w @(d:16,ers), rd mov.w @(d:24,ers), rd mov.w @ers+, rd mov.w @aa:16, rd mov.w @aa:24, rd mov.w rs, @erd mov.w rs, @(d:16,erd) mov.w rs, @(d:24,erd) 2 3 2 1 1 2 4 1 2 3 1 2 4 1 1 1 1 1 1 1 1 1 1 1 2
appendix rev. 3.00 sep. 10, 2007 page 485 of 528 rej09b0216-0300 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n mov mov.w rs, @-erd mov.w rs, @aa:16 mov.w rs, @aa:24 mov.l #xx:32, erd mov.l ers, erd mov.l @ers, erd mov.l @(d:16,ers), erd mov.l @(d:24,ers), erd mov.l @ers+, erd mov.l @aa:16, erd mov.l @aa:24, erd mov.l ers,@erd mov.l ers, @(d:16,erd) mov.l ers, @(d:24,erd) mov.l ers, @-erd mov.l ers, @aa:16 mov.l ers, @aa:24 1 2 3 3 1 2 3 5 2 3 4 2 3 5 2 3 4 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 movfpe movfpe @aa:16, rd * 2 2 1 movtpe movtpe rs,@aa:16 * 2 2 1 mulxs mulxs.b rs, rd mulxs.w rs, erd 2 2 12 20 mulxu mulxu.b rs, rd mulxu.w rs, erd 1 1 12 20 neg neg.b rd neg.w rd neg.l erd 1 1 1 nop nop 1 not not.b rd not.w rd not.l erd 1 1 1
appendix rev. 3.00 sep. 10, 2007 page 486 of 528 rej09b0216-0300 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n or or.b #xx:8, rd or.b rs, rd or.w #xx:16, rd or.w rs, rd or.l #xx:32, erd or.l ers, erd 1 1 2 1 3 2 orc orc #xx:8, ccr 1 pop pop.w rn pop.l ern 1 2 1 2 2 2 push push.w rn push.l ern 1 2 1 2 2 2 rotl rotl.b rd rotl.w rd rotl.l erd 1 1 1 rotr rotr.b rd rotr.w rd rotr.l erd 1 1 1 rotxl rotxl.b rd rotxl.w rd rotxl.l erd 1 1 1 rotxr rotxr.b rd rotxr.w rd rotxr.l erd 1 1 1 rte rte 2 2 2 rts rts 2 1 2 shal shal.b rd shal.w rd shal.l erd 1 1 1 shar shar.b rd shar.w rd shar.l erd 1 1 1
appendix rev. 3.00 sep. 10, 2007 page 487 of 528 rej09b0216-0300 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n shll shll.b rd shll.w rd shll.l erd 1 1 1 shlr shlr.b rd shlr.w rd shlr.l erd 1 1 1 sleep sleep 1 stc stc ccr, rd stc ccr, @erd stc ccr, @(d:16,erd) stc ccr, @(d:24,erd) stc ccr,@-erd stc ccr, @aa:16 stc ccr, @aa:24 1 2 3 5 2 3 4 1 1 1 1 1 1 2 sub sub.b rs, rd sub.w #xx:16, rd sub.w rs, rd sub.l #xx:32, erd sub.l ers, erd 1 2 1 3 1 subs subs #1/2/4, erd 1 subx subx #xx:8, rd subx. rs, rd 1 1 trapa trapa #xx:2 2 1 2 4 xor xor.b #xx:8, rd xor.b rs, rd xor.w #xx:16, rd xor.w rs, rd xor.l #xx:32, erd xor.l ers, erd 1 1 2 1 3 2 xorc xorc #xx:8, ccr 1 notes: 1. n: specified value in r4l and r4. the source and destination operands are accessed n+1 times respectively. 2. cannot be used in this lsi.
appendix rev. 3.00 sep. 10, 2007 page 488 of 528 rej09b0216-0300 a.4 combinations of instructions and addressing modes table a.5 combinations of instructions and addressing modes addressing mode mov pop, push movfpe, movtpe add, cmp sub addx, subx adds, subs inc, dec daa, das mulxu, mulxs, divxu, divxs neg extu, exts and, or, xor not bcc, bsr jmp, jsr rts trapa rte sleep ldc stc andc, orc, xorc nop data transfer instructions arithmetic operations logical operations shift operations bit manipulations branching instructions system control instructions block data transfer instructions bwl ? ? bwl wl b ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? b ? b ? ? #xx rn @ern @(d:16.ern) @(d:24.ern) @ern+/@ern @aa:8 @aa:16 @aa:24 @(d:8.pc) @(d:16.pc) @@aa:8 ? bwl ? ? bwl bwl b l bwl b bw bwl wl bwl bwl bwl b ? ? ? ? ? ? b b ? ? ? bwl ? ? ? ? ? ? ? ? ? ? ? ? ? ? b ? ? ? ? ? w w ? ? ? bwl ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? w w ? ? ? bwl ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? w w ? ? ? bwl ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? w w ? ? ? b ? ? ? ? ? ? ? ? ? ? ? ? ? ? b ? ? ? ? ? ? ? ? ? ? ? bwl ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? w w ? ? ? bwl ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? w w ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? wl ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bw functions instructions
appendix rev. 3.00 sep. 10, 2007 page 489 of 528 rej09b0216-0300 appendix b i/o port block diagrams b.1 i/o port block diagrams res goes low in a reset, and sby goes low at reset and in standby mode. pdr pucr pmr pcr sby res pucr: port pull-up control register pmr: port mode register pdr: port data register pcr: port control register irq trgv internal data bus pull-up mos [legend] figure b.1 port 1 block diagram (p17)
appendix rev. 3.00 sep. 10, 2007 page 490 of 528 rej09b0216-0300 pdr pucr pmr pcr sby res pucr: port pull-up control register pmr: port mode register pdr: port data register pcr: port control register irq internal data bus pull-up mos [legend] figure b.2 port 1 block diagram (p14, p16)
appendix rev. 3.00 sep. 10, 2007 page 491 of 528 rej09b0216-0300 pdr pucr pmr pcr sby res [legend] pucr : pmr : pdr : pcr : port pull-up control register port mode register port data register port control register internal data bus pull-up mos irq tmib1 figure b.3 port 1 block diagram (p15)
appendix rev. 3.00 sep. 10, 2007 page 492 of 528 rej09b0216-0300 pdr pucr pcr sby res [legend] pucr : pdr : pcr : port pull-up control register port data register port control register internal data bus pull-up mos figure b.4 port 1 block diagram (p12)
appendix rev. 3.00 sep. 10, 2007 page 493 of 528 rej09b0216-0300 pdr pucr pmr pcr sby res pwm 14-bit pwm internal data bus pull-up mos [legend] pucr : pmr : pdr : pcr : port pull-up control register port mode register port data register port control register figure b.5 port 2 block diagram (p11)
appendix rev. 3.00 sep. 10, 2007 page 494 of 528 rej09b0216-0300 pdr pucr pmr pcr sby res pucr : pmr : pdr : pcr : [legend] port pull-up control register port mode register port data register port control register internal data bus pull-up mos tmow rtc figure b.6 port 1 block diagram (p10)
appendix rev. 3.00 sep. 10, 2007 page 495 of 528 rej09b0216-0300 pdr pmr pcr sby pmr : pdr : pcr : [legend] port mode register port data register port control register internal data bus figure b.7 port 2 block diagram (p24, p23)
appendix rev. 3.00 sep. 10, 2007 page 496 of 528 rej09b0216-0300 pdr pmr pcr sby txd sci3 pmr : pdr : pcr : [legend] port mode register port data register port control register internal data bus figure b.8 port 2 block diagram (p22)
appendix rev. 3.00 sep. 10, 2007 page 497 of 528 rej09b0216-0300 pdr pcr sby pdr: port data register pcr: port control register re internal data bus rxd sci3 [legend] figure b.9 port 2 block diagram (p21)
appendix rev. 3.00 sep. 10, 2007 page 498 of 528 rej09b0216-0300 pdr pcr sby pdr: port data register pcr: port control register sckie internal data bus scki sci3 sckoe scko [legend] figure b.10 port 2 block diagram (p20)
appendix rev. 3.00 sep. 10, 2007 page 499 of 528 rej09b0216-0300 pdr pcr sby [legend] pdr : pcr : port data register port control register internal data bus figure b.11 port 3 block diagram (p37 to p30)
appendix rev. 3.00 sep. 10, 2007 page 500 of 528 rej09b0216-0300 pdr pmr pcr sby ice sdao/sclo sdai/scli iic2 pmr : pdr : pcr : port mode register port data register port control register internal data bus [legend] figure b.12 port 5 block diagram (p57, p56)
appendix rev. 3.00 sep. 10, 2007 page 501 of 528 rej09b0216-0300 pdr pucr pmr pcr sby res pucr: port pull-up control register pmr: port mode register pdr: port data register pcr: port control register wkp internal data bus adtrg pull-up mos [legend] figure b.13 port 5 block diagram (p55)
appendix rev. 3.00 sep. 10, 2007 page 502 of 528 rej09b0216-0300 pdr pucr pmr pcr sby res pucr: port pull-up control register pmr: port mode register pdr: port data register pcr: port control register wkp internal data bus pull-up mos [legend] figure b.14 port 5 block diagram (p54 to p50)
appendix rev. 3.00 sep. 10, 2007 page 503 of 528 rej09b0216-0300 pdr pcr sby pdr : pcr : port data register port control register [legend] ftioa to ftiod output control signals a to d timer z internal data bus figure b.15 port 6 block diagram (p67 to p60)
appendix rev. 3.00 sep. 10, 2007 page 504 of 528 rej09b0216-0300 pdr pcr sby os3 os2 os1 os0 tmov pdr: port data register pcr: port control register internal data bus timer v [legend] figure b.16 port 7 block diagram (p76)
appendix rev. 3.00 sep. 10, 2007 page 505 of 528 rej09b0216-0300 pdr pcr sby tmciv pdr: port data register pcr: port control register internal data bus timer v [legend] figure b.17 port 7 block diagram (p75)
appendix rev. 3.00 sep. 10, 2007 page 506 of 528 rej09b0216-0300 pdr pcr sby tmriv pdr: port data register pcr: port control register internal data bus timer v [legend] figure b.18 port 7 block diagram (p74)
appendix rev. 3.00 sep. 10, 2007 page 507 of 528 rej09b0216-0300 pdr pmr pcr sby [legend] pmr : pdr : pcr : port mode register port data register port control register internal data bus txd sci3_2 figure b.19 port 7 block diagram (p72)
appendix rev. 3.00 sep. 10, 2007 page 508 of 528 rej09b0216-0300 pdr pcr sby re rxd sci3_2 [legend] pdr : pcr : port data register port control register internal data bus figure b.20 port 7 block diagram (p71) pdr pcr sby sckie scki sci3_2 sckoe scko [legend] pdr : pcr : port data register port control register internal data bus figure b.21 port 7 block diagram (p70)
appendix rev. 3.00 sep. 10, 2007 page 509 of 528 rej09b0216-0300 pdr pcr sby pdr: port data register pcr: port control register internal data bus [legend] figure b.22 port 8 block diagram (p87 to p85)
appendix rev. 3.00 sep. 10, 2007 page 510 of 528 rej09b0216-0300 dec vin scan ch3 to ch0 a/d converter extd, extu vddii low voltage detection circuit internal data bus figure b.23 port b block diagram (pb7 and pb6) dec scan ch3 to ch0 vin a/d converter internal data bus figure b.24 port b block diagram (pb5 to pb0)
appendix rev. 3.00 sep. 10, 2007 page 511 of 528 rej09b0216-0300 pdr pcr sby internal data bus pmrc1 pmrc0 xtali cpg [legend] pdr: port data register pcr: port control register figure b.25 port b block diagram (pc1)
appendix rev. 3.00 sep. 10, 2007 page 512 of 528 rej09b0216-0300 pdr pcr sby internal data bus pmrc0 extali cpg pdr: pcr: port data register port control register [legend] figure b.26 port b block diagram (pc0)
appendix rev. 3.00 sep. 10, 2007 page 513 of 528 rej09b0216-0300 b.2 port states in ea ch operating state port reset sleep subsleep standby subactive active p17 to p14, p12 to p10 high impedance retained retained high impedance * functioning functioning p24 to p20 high impedance retained retained high impedance functioning functioning p37 to p30 high impedance retained retained high impedance functioning functioning p57 to p50 high impedance retained retained high impedance * functioning functioning p67 to p60 high impedance retained retained high impedance functioning functioning p76 to p74, p72 to p70 high impedance retained retained high impedance functioning functioning p87 to p85 high impedance retained retained high impedance functioning functioning pb7 to pb0 high impedance high impedance high impedance high impedance high impedance high impedance pc1 and pc0 high impedance retained retained high impedance functioning functioning note: * high level output when the pull-up mos is turned on.
appendix rev. 3.00 sep. 10, 2007 page 514 of 528 rej09b0216-0300 appendix c product code lineup product classification product group voltage specification * 1 temperature specification * 2 product code * 3 model marking package (package code) regular hd64f36079gh hd64f36079gh wide range hd64f36079ghw hd64f36079ghw qfp-64 (fp-64a) regular hd64f36079gfz hd64f36079gfz h8/36079gf 5.0 v wide range hd64f36079gfzw hd64f36079gfzw lqfp-64 (fp-64k) regular hd64f36079lh hd64f36079lh wide range hd64f36079lhw hd64f36079lhw qfp-64 (fp-64a) regular hd64f36079lfz hd64f36079lfz h8/36079lf 3.3 v wide range hd64f36079lfzw hd64f36079lfzw lqfp-64 (fp-64k) regular hd64f36078gh hd64f36078gh wide range hd64f36078ghw hd64f36078ghw qfp-64 (fp-64a) regular hd64f36078gfz hd64f36078gfz h8/36078gf 5.0 v wide range hd64f36078gfzw hd64f36078gfzw lqfp-64 (fp-64k) regular hd64f36078lh hd64f36078lh wide range hd64f36078lhw hd64f36078lhw qfp-64 (fp-64a) regular hd64f36078lfz hd64f36078lfz flash memory version h8/36079 group h8/36078lf 3.3 v wide range hd64f36078lfzw hd64f36078lfzw lqfp-64 (fp-64k)
appendix rev. 3.00 sep. 10, 2007 page 515 of 528 rej09b0216-0300 product classification product group voltage specification * 1 temperature specification * 2 product code * 3 model marking package (package code) regular hd64f36077gh hd64f36077gh wide range hd64f36077ghw hd64f36077ghw qfp-64 (fp-64a) regular hd64f36077gfz hd64f36077gfz h8/36077gf 5.0 v wide range hd64f36077gfzw hd64f36077gfzw lqfp-64 (fp-64k) regular hd64f36077lh hd64f36077lh wide range hd64f36077lhw hd64f36077lhw qfp-64 (fp-64a) regular hd64f36077lfz hd64f36077lfz h8/36077lf 3.3 v wide range hd64f36077lfzw hd64f36077lfzw lqfp-64 (fp-64k) regular HD64F36074Gh HD64F36074Gh wide range HD64F36074Ghw HD64F36074Ghw qfp-64 (fp-64a) regular HD64F36074Gfz HD64F36074Gfz h8/36074gf 5.0 v wide range HD64F36074Gfzw HD64F36074Gfzw lqfp-64 (fp-64k) regular hd64f36074lh hd64f36074lh wide range hd64f36074lhw hd64f36074lhw qfp-64 (fp-64a) regular hd64f36074lfz hd64f36074lfz flash memory version h8/36077 group h8/36074lf 3.3 v wide range hd64f36074lfzw hd64f36074lfzw lqfp-64 (fp-64k) notes: 1. operating voltage range: 4.5 to 5.5 v (5.0-v models), 3.0 to 3.6 v (3.3-v models) 2. operating temperature range: regular specifications: -20 to +75c, wide-range specifications: -40 to +85c 3. the table includes products that are yet to be released. for details, please contact one of our sales representatives.
appendix rev. 3.00 sep. 10, 2007 page 516 of 528 rej09b0216-0300 appendix d package dimensions terminal cross section b 1 c 1 b p c 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. index mark * 3 17 32 64 49 116 33 48 f * 1 * 2 x y b p h e e h d d z d z e detail f a c a 2 a 1 l 1 l p-lqfp64-10x10-0.50 0.3g mass[typ.] 64p6q-a / fp-64k / fp-64kv plqp0064kb-a renesas code jeita package code previous code 1.0 0.125 0.18 1.25 1.25 0.08 0.20 0.145 0.09 0.25 0.20 0.15 max nom min dimension in millimeters symbol reference 10.1 10.0 9.9 d 10.1 10.0 9.9 e 1.4 a 2 12.2 12.0 11.8 12.2 12.0 11.8 1.7 a 0.15 0.1 0.05 0.65 0.5 0.35 l x 8 0 c 0.5 e 0.08 y h d h e a 1 b p b 1 c 1 z d z e l 1 e figure d.1 fp-64k package dimensions
appendix rev. 3.00 sep. 10, 2007 page 517 of 528 rej09b0216-0300 note) 1. dimensions"*1"and"*2" do not include mold flash 2. dimension"*3"does not include trim offset. * 1 * 2 * 3 p e d e d xm y f 64 1 17 16 49 48 32 33 z z d h e h b 2 1 1 detail f c a a l a l terminal cross section p 1 1 c b c b prqp0064gb-a p-qfp64-14x14-0.80 0.8 1.0 1.0 0.15 0.10 8 0 0.25 0.10 0.15 0.35 0.00 0.45 0.37 0.29 0.22 0.17 0.12 3.05 16.9 17.2 17.5 d 1 e d 1 1 p 1 e d 2 l z z y x c b b a h a e a c e e l h 1.2g mass[typ.] fp-64a/fp-64av renesas code jeita package code previous code 1.1 0.8 0.5 max nom min dimension in millimeters symbol reference 14 2.70 17.5 17.2 16.9 1.6 14 figure d.2 fp-64a package dimensions
appendix rev. 3.00 sep. 10, 2007 page 518 of 528 rej09b0216-0300
rev. 3.00 sep. 10, 2007 page 519 of 528 rej09b0216-0300 main revisions and additions in this edition item page revision (see manual for details) section 7 rom 7.6 programmer mode 127 amended in programmer mode, a prom programmer can be used to perform programming/erasing via a socket adapter, just as a discrete flash memory. use a prom programmer that supports the mcu device type with the on-chip 128-kbyte flash memory (fztat64v5). section 16 serial communication interface 3 (sci3) table 16.3 examples of brr settings for various bit rates (asynchronous mode) (3) 299 amended operating frequency ? (mhz) 12.288 14 bit rate (bit/s) n n error (%) n n error (%) section 18 a/d converter figure 18.1 block diagram of a/d converter 368 deleted control circuit ?/4 ?/8 section 21 list of registers 405 amended register name bit 7 ? : : : flpwcr pdwnd : ebr1 * 1 eb7 : notes: 4. the bit configuration of ebr1 differs according to products. for the bit configuration of each product, see the list below.
rev. 3.00 sep. 10, 2007 page 520 of 528 rej09b0216-0300 item page revision (see manual for details) section 21 list of registers 408 added h8/3609g,h8/36079l register name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 module name ebr1 eb7 eb6 eb5 eb4 eb3 eb2 eb1 eb0 rom h8/36078g,h8/36078l,h8/36077g,h8/36077l register name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 module name ebr1 ? eb6 eb5 eb4 eb3 eb2 eb1 eb0 rom h8/36074g,h8/36074l register name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 module name ebr1 ? ? ? eb4 eb3 eb2 eb1 eb0 rom section 22 electrical characteristics 415 to 458 the wide temperature range of ta = ?40 to +85c is added to the conditions. table 22.3 ac characteristics 427 amended values item test condition min. typ. min. vcc = 5.0 v ta = 25 c fsel= 1 vclsel= 0 19.70 20.0 20.30 fsel = 1, ta = -20 to +75 c, vclsel = 0 19.40 20.0 20.60 fsel = 1, ta = -40 to +85 c, vclsel = 0 19.20 20.00 20.80 vcc = 5.0 v, ta = 25 c, fsel = 0, vclsel = 0 15.76 16.0 16.24 fsel = 0, ta = -20 to +75 c, vclsel = 0 15.52 16.0 16.48 on-chip oscillator oscillation frequency fsel = 0, ta = -40 to +85 c, vclsel = 0 15.36 16.0 16.64
rev. 3.00 sep. 10, 2007 page 521 of 528 rej09b0216-0300 item page revision (see manual for details) table 22.6 a/d converter characteristics 431 amended values item min typ max conversion time (single mode) 134 ? ? nonlinearity error ? ? 3.5 offset error ? ? 3.5 full-scale error ? ? 3.5 quantization error ? ? 0.5 absolute accuracy ? ? 4.0 table 22.9 power-supply- voltage detection circuit characteristics 434 amended values item min typ max reset detection voltage 2* 2 3.3 3.6 3.9 amended values item symbol min typ max : : : : : : pull-up mos current ?i p ? 60.0 ? table 22.12 dc characteristics (1) 440 amended values item symbol min typ max : : : : : : : : : : : ? 2.8 4.0 active mode current consumption i ope2 ? 2.5 ?
rev. 3.00 sep. 10, 2007 page 522 of 528 rej09b0216-0300 item page revision (see manual for details) table 22.13 ac characteristics 446 amended values item test condition min. typ. min. vcc = 3.3 v ta = 25 c fsel= 1 vclsel= 0 19.70 20.00 20.30 fsel = 1, ta = -20 to +75 c, vclsel = 0 19.40 20.00 20.60 fsel = 1, ta = -40 to +85 c, vclsel = 0 19.2 20.0 20.8 vcc = 3.3 v, ta = 25 c, fsel = 0, vclsel = 0 15.76 16.00 16.24 fsel = 0, ta = -20 to +75 c, vclsel = 0 15.36 16.0 16.64 on-chip oscillator oscillation frequency fsel = 0, ta = -40 to +85 c, vclsel = 0 15.52 16.0 16.48 table 22.19 power-supply- voltage detection circuit characteristics 453 amended values item min. min. min. power-supply falling detection voltage 2.8 2.9 3.05 power-supply rising detection voltage 2.9 3.0 3.15
rev. 3.00 sep. 10, 2007 page 523 of 528 rej09b0216-0300 item page revision (see manual for details) appendix c product code lineup 515 amended product cl assification product group voltage specificat ion*1 temperature specification *2 product code*3 model marking p ackage (package code) regular hd64f36079gh hd64f36079gh wide range hd64f36079ghw hd64f36079ghw qfp-64 (fp-64a) regular hd64f36079gfz hd64f36079gfz h8/36079gf 5.0 v wide range hd64f36079gfzw hd64f36079gfzw lqfp-64 (fp-64k) regular hd64f36079lh hd64f36079lh wide range hd64f36079lhw hd64f36079lhw qfp-64 (fp-64a) regular hd64f36079lfz hd64f36079lfz h8/36079lf 3.3 v wide range hd64f36079lfzw hd64f36079lfzw lqfp-64 (fp-64k) regular hd64f36078gh hd64f36078gh wide range hd64f36078ghw hd64f36078ghw qfp-64 (fp-64a) regular hd64f36078gfz hd64f36078gfz h8/36078gf 5.0 v wide range hd64f36078gfzw hd64f36078gfzw lqfp-64 (fp-64k) regular hd64f36078lh hd64f36078lh wide range hd64f36078lhw hd64f36078lhw qfp-64 (fp-64a) regular hd64f36078lfz hd64f36078lfz h8/36079 group h8/36078lf 3.3 v wide range hd64f36078lfzw hd64f36078lfzw lqfp-64 (fp-64k)
rev. 3.00 sep. 10, 2007 page 524 of 528 rej09b0216-0300 item page revision (see manual for details) appendix c product code lineup 516 amended product cl assification product group voltage specification *1 product code*3 model marking p ackage (package code) regular hd64f36077gh hd64f36077gh wide range hd64f36077ghw hd64f36077ghw qfp-64 (fp-64a) regular hd64f36077gfz hd64f36077gfz h8/36077gf 5.0 v wide range hd64f36077gfzw hd64f36077gfzw lqfp-64 (fp-64k) regular hd64f36077lh hd64f36077lh wide range hd64f36077lhw hd64f36077lhw qfp-64 (fp-64a) regular hd64f36077lfz hd64f36077lfz h8/36077lf 3.3 v wide range hd64f36077lfzw hd64f36077lfzw lqfp-64 (fp-64k) regular HD64F36074Gh HD64F36074Gh wide range HD64F36074Ghw HD64F36074Ghw qfp-64 (fp-64a) regular HD64F36074Gfz HD64F36074Gfz h8/36074gf 5.0 v wide range HD64F36074Gfzw HD64F36074Gfzw lqfp-64 (fp-64k) regular hd64f36074lh hd64f36074lh wide range hd64f36074lhw hd64f36074lhw qfp-64 (fp-64a) h8/36077 group h8/36074lf 3.3 v regular hd64f36074lfz hd64f36074lfz lqfp-64 (fp-64k)
rev. 3.00 sep. 10, 2007 page 525 of 528 rej09b0216-0300 index numerics 14-bit pw m ............................................ 281 a a/d converter ......................................... 367 absolute address....................................... 31 acknowle dge .......................................... 346 address break ........................................... 63 addressing modes..................................... 30 arithmetic operations instructions............ 21 asynchronou s mode ............................... 303 auto-reload timer operation.................... 183 b bit manipulation instructions.................... 24 bit rate .................................................... 296 bit synchronou s circuit ........................... 363 block data transfer instructions ................ 28 boot m ode............................................... 117 boot prog ram.......................................... 117 branch instructions ................................... 26 break....................................................... 326 buffer operation...................................... 254 c clock synchron ous mode........................ 311 clock synchronous serial format ............ 354 complementary pwm mode .................. 244 condition field .......................................... 29 condition-code register (ccr)................. 14 cpu ............................................................ 9 d data reading procedure ........................... 177 data transfer instructions .......................... 20 e effective address ....................................... 33 effective address extension....................... 29 erase/erase-verify ................................... 124 erasing units ........................................... 107 error protection....................................... 126 event counter operation .......................... 183 exception handling ................................... 45 f flash memory.......................................... 107 framing error .......................................... 307 g general registers ....................................... 13 h hardware protection................................ 126 i i/o port block diagrams .......................... 489 i/o ports .................................................. 131 i 2 c bus format ......................................... 345 i 2 c bus interface 2 (iic2)........................ 329 immediate ................................................. 32 initial setting procedure .......................... 176 input capture function ............................. 229 instruction set............................................ 19
rev. 3.00 sep. 10, 2007 page 526 of 528 rej09b0216-0300 internal interrupts ..................................... 58 internal power supply step-down circuit .................................... 393 interrupt mask bit...................................... 15 interrupt response time ............................. 60 interval timer operation .......................... 182 irq3 to irq0 interrupts ........................... 56 l large current ports...................................... 3 logic operations instructions.................... 23 low-voltage detection circuit ................. 379 lvdi (interrupt by low voltage detect) circuit.............................................. 389, 390 lvdr (reset by low voltage detect) circuit...................................................... 387 m memory indirect ....................................... 32 memory map ............................................ 11 module standby function ........................ 106 multiprocessor communication function................................................... 318 n nmi interrupt............................................ 56 noise canceler ........................................ 357 o on-board progra mming modes............... 117 operation field.......................................... 29 overrun error .......................................... 307 p package ....................................................... 3 package dimensions ................................ 516 parity error .............................................. 307 pin arrangement .......................................... 5 power-down modes................................... 93 power-down states .................................. 127 power-on reset ........................................ 379 power-on reset circuit ............................. 386 product code lineup ................................ 514 program counter (pc) ............................... 14 program/program-verify ......................... 121 program-counter relative .......................... 32 programmer mode................................... 127 programming units.................................. 107 programming/erasing in user progra m mode ................................. 120 pwm mode ............................................. 234 r realtime clock (rtc) ............................. 167 register direct ........................................... 30 register field............................................. 29 register indirect ........................................ 31 register indirect with displacement .......... 31 register indirect with post-increment ....... 31 register indirect with pre-decrement ........ 31 register settings ...................................... 284 registers abrkcr ...................... 64, 4 00, 406, 411 abrksr ...................... 67, 4 00, 406, 411 adcr ......................... 372, 400, 406, 411 adcsr ....................... 371, 399, 406, 411 addra ...................... 370, 399, 406, 411 addrb ...................... 370, 399, 406, 411 addrc ...................... 370, 399, 406, 411 addrd ...................... 370, 399, 406, 411 bare............................ 67, 4 00, 406, 412 barh ........................... 67, 4 00, 406, 412
rev. 3.00 sep. 10, 2007 page 527 of 528 rej09b0216-0300 barl............................ 67, 4 00, 406, 412 bdrh ........................... 67, 4 00, 406, 412 bdrl............................ 67, 4 00, 406, 412 brr ............................ 296, 399, 405, 411 ckcsr ......................... 76, 3 97, 404, 410 ebr1 .......................... 114, 399, 405, 411 fenr .......................... 116, 399, 405, 411 flmcr1..................... 112, 398, 405, 411 flmcr2..................... 113, 398, 405, 411 flpwcr .................... 116, 398, 405, 411 gra............................ 213, 396, 403, 409 grb ............................ 213, 396, 403, 409 grc ............................ 213, 396, 403, 409 grd............................ 213, 396, 403, 409 iccr1......................... 332, 398, 405, 410 iccr2......................... 335, 398, 405, 410 icdrr ........................ 344, 398, 405, 410 icdrs ................................................ 344 icdrt ........................ 344, 398, 405, 410 icier.......................... 338, 398, 405, 410 icmr .......................... 336, 398, 405, 410 icsr ........................... 340, 398, 405, 410 iegr1........................... 48, 401, 407, 413 iegr2........................... 49, 401, 407, 413 ienr1........................... 50, 401, 407, 413 ienr2........................... 51, 401, 407, 413 irr1 ............................. 51, 4 01, 407, 413 irr2 ............................. 53, 4 02, 407, 413 iwpr ............................ 53, 4 02, 407, 413 lvdcr....................... 382, 397, 404, 410 lvdrf ....................... 385, 397, 404, 410 lvdsr ....................... 384, 397, 404, 410 mstcr1....................... 98, 402, 408, 413 mstcr2....................... 99, 402, 408, 413 pcr1........................... 133, 401, 407, 412 pcr2........................... 137, 401, 407, 412 pcr3........................... 141, 401, 407, 412 pcr5........................... 147, 401, 407, 412 pcr6........................... 151, 401, 407, 412 pcr7........................... 156, 401, 407, 412 pcr8........................... 159, 401, 407, 412 pcrc .......................... 165, 401, 407, 412 pdr1........................... 133, 400, 406, 412 pdr2........................... 138, 400, 407, 412 pdr3........................... 142, 400, 407, 412 pdr5........................... 147, 400, 407, 412 pdr6........................... 152, 401, 407, 412 pdr7........................... 157, 401, 407, 412 pdr8........................... 159, 401, 407, 412 pdrb .......................... 161, 401, 407, 412 pdrc .......................... 166, 401, 407, 412 pmr1 .......................... 132, 401, 407, 412 pmr3 .......................... 138, 401, 407, 412 pmr5 .......................... 146, 401, 407, 412 pocr .......................... 221, 396, 403, 409 pucr1 ........................ 134, 400, 406, 412 pucr5 ........................ 148, 400, 406, 412 pwcr ......................... 283, 400, 406, 411 pwdrl ...................... 283, 400, 406, 411 pwdru ...................... 283, 400, 406, 411 rccr............................ 73, 3 97, 404, 410 rctrmdpr................. 74, 397, 404, 410 rctrmdr ................... 75, 398, 404, 410 rdr ............................ 289, 399, 406, 411 rhrdr....................... 171, 397, 404, 410 rmindr..................... 170, 397, 404, 410 rsecdr ..................... 169, 397, 404, 410 rsr..................................................... 289 rtccr1 ..................... 173, 397, 404, 410 rtccr2 ..................... 174, 397, 404, 410 rtccsr ..................... 175, 397, 404, 410 rwkdr...................... 172, 397, 404, 410 sar............................. 343, 398, 405, 410 scr3........................... 292, 399, 405, 411 smr ............................ 290, 399, 405, 411 ssr ............................. 294, 399, 406, 411 syscr1........................ 94, 4 01, 407, 412 syscr2........................ 97, 4 01, 407, 412 tcb1........................... 182, 398, 405, 410 tcnt .......................... 213, 396, 403, 409
rev. 3.00 sep. 10, 2007 page 528 of 528 rej09b0216-0300 tcntv........................187, 399, 405, 411 tcora........................188, 399, 405, 411 tcorb........................188, 399, 405, 411 tcr .............................214, 396, 403, 409 tcrv0 ........................188, 399, 405, 411 tcrv1 ........................191, 399, 405, 411 tcsrv ........................189, 399, 405, 411 tcsrwd ....................276, 400, 406, 411 tcwd .........................278, 400, 406, 411 tdr .............................290, 399, 406, 411 tfcr ...........................208, 397, 404, 409 tier ............................220, 396, 403, 409 tiora.........................215, 396, 403, 409 tiorc .........................216, 396, 403, 409 tlb1............................182, 398, 405, 410 tmb1 ..........................181, 398, 405, 410 tmdr..........................206, 397, 404, 409 tmwd ........................278, 400, 406, 411 tocr ..........................212, 397, 404, 409 toer...........................210, 397, 404, 409 tpmr ..........................207, 397, 404, 409 tsr..............................218, 396, 403, 409 tstr ...........................206, 397, 404, 409 reset exception handling.......................... 55 reset synchronous pwm mode.............. 240 s sample-and-hold circuit ......................... 374 scan mode .............................................. 373 serial communication interface 3 (sci3) ................................... 285 shift instructions....................................... 23 single mode ............................................ 373 slave address........................................... 346 sleep mode.............................................. 103 software protection................................. 126 stack pointer (sp) ..................................... 14 stack status ............................................... 59 standby mode ......................................... 103 start condition......................................... 346 stop condition ......................................... 346 subactive mode....................................... 104 subsleep mode ........................................ 104 synchronous operation............................ 233 system clocks ........................................... 71 system control instructions....................... 27 system prescaler s .................................... 91 t timer b1................................................. 179 timer v................................................... 185 timer z ................................................... 199 transfer rate............................................ 334 trap instruction......................................... 45 v vector address........................................... 46 w watchdog timer....................................... 275 waveform output .................................... 284 waveform output by compare match...... 227 wkp5 to wkp0 interrupts ....................... 56
renesas 16-bit single-chip microcomputer hardware manual h8/36079 group, h8/36077 group publication date: rev.1.00, sep. 16, 2005 rev.3.00, sep. 10, 2007 published by: sales strategic planning div. renesas technology corp. edited by: customer support department global strategic communication div. renesas solutions corp. ? 2007. renesas technology corp., all rights reserved. printed in japan.
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h8/36079 group, h8/36077 group rej09b0216-0300 hardware manual 1753, shimonumabe, nakahara-ku, kawasaki-shi, kanagawa 211-8668 japan

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